Configurable Central Clock and Reset Controller

Abstract

With growing complexity of developing Application-Specific Integrated Circuit
(ASIC), comes a higher development time, in both designing and verifying Reg-
ister Transfer Level (RTL) code. Configurability can reduce the time spent on
re-designing, and instead replace with simple reconfiguration. The configurable
design then typically need initial verification effort.
This thesis seeks to investigate the possibilities of making the Clock and Reset
Controller (CCR) block more configurable, both in terms of run-time and compile-
time configurability. The configurability makes the interface and logic of modules
more predictable which more easily enable reusability in the verification frame-
work. However, as concluded in the thesis, using SystemVerilog language features
for configurability can reduce the readability of the RTL code. Code generation
can be used to generate more readable RTL files, but can be harder to implement.
The thesis investigates different run-time Finite State Machine (FSM) architec-
tures suitable for CCR, and choses one for implementation. The results show that
the design sets constraints on the functionalities of the FSM and can come with
increased area and power, but can save from expensive re-tapeouts in case of faulty
implemented logic.
Clock division and clock muxing are critical features used throughout the CCR.
The thesis investigates current clock division and clock muxing designs and pro-
poses new implementations, that can be configured for in the CCR. The proposed
clock mux implementation has less area, power, critical path and faster transi-
tion time, than using traditional 2 input glitch free multiplexers, according to our
measurements. However, more testing would need to be done.
One technique to integrate third-party Intellectual Propertys (IPs) is to design
a wrapper module. A unified Phase-Locked Loop (PLL) wrapper interface was
designed, that can integrate a variety of PLLs. The thesis also proposes a gen-
eral software automation flow, where code generation is used to integrate a PLL
wrapper, through defining pin connections and configurations in a spreadsheet.

Popular Abstract

In modern electronic systems, it is common to see the inclusion of one or many
ASICs, which are "chips" developed for specific tasks. Inside the ASIC, there are
numerous logical modules called IP, which handles some functionality of the ASIC.
This thesis explores one such IP at Ericsson called CCR. Clocks are essential to
the ASIC and allows for determinism, robustness, synchronisation and data pipe-
lining. Reset signals ensure that the ASIC go to a deterministic state, which is
particularly useful when booting up the ASIC. The CCR ensures that other IPs
receive stable clocks and reset.
The IPs in an ASIC are designed using hardware description languages. These
languages allows the designer to describe how the IP should function, using RTL
code. One popular RTL coding language called SystemVerilog includes features
to design configurable code. This means that the code can adapt to changes
in its specification, without writing new code to describe the new functionality.
Configurability can avoid redesign of the IP, which can reduce the development
time and reduce human-made errors. This thesis explores the possibility of making
the CCR IP more configurable.
The results show that making a configurable IP comes with challenges and trade-
offs. One such trade-off is that the readability of the RTL code can be worse when
making it configurable. Another challenge is making the design configurable while
the ASIC is running, as this can increase the area and power consumption.
The thesis can be used by ASIC RTL design engineers seeking to learn about tech-
niques used and the trade-offs of designing configurable RTL code, such as using
software scripts to generate RTL code. The thesis also proposes new implementa-
tions that can be used when constructing designs similar to the CCR.

• author: Tegnvallius Boklund, Alexander and Strömberg, Ture
• supervisor: Liang Liu
• organization: Department of Electrical and Information Technology
• course: EITM01 20261
• year: 2026
• type: H1 - Master's Degree (One Year)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2026-1133
• language: English
• id: 9234901
• date added to LUP: 2026-06-11 11:14:32
• date last changed: 2026-06-11 11:14:32