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Direct RF sampling ADC analog front-end for 6G

Callmar, Theodor LU and Andréasson, Olof (2026) EITM01 20261
Department of Electrical and Information Technology
Abstract
A time-interleaved ADC analog front-end is presented with a sampling rate of
64GS/s. It has a hierarchical architecture of 2-4-4 giving 32 separate channels.
Each channel is constructed by an input buffer, 1st rank (T/H), sub-buffer, and 2nd
rank T/H. The complimentary clocking generation consist of a 32GHz differential
signal divided down using a CML divide-by-4 and DFF divide-by-4 architecture.
The required duty cycles for the time-interleaved network were generated using
gate logic. The SFDR and SNR ranges from 41dBc-34dBc and 38dB-31dB re-
spectively within the FR3 band. In stable state, the total power consumption of
the analog front-end is 484mW including the interleaving network and clock gen-
eration. This was constructed... (More)
A time-interleaved ADC analog front-end is presented with a sampling rate of
64GS/s. It has a hierarchical architecture of 2-4-4 giving 32 separate channels.
Each channel is constructed by an input buffer, 1st rank (T/H), sub-buffer, and 2nd
rank T/H. The complimentary clocking generation consist of a 32GHz differential
signal divided down using a CML divide-by-4 and DFF divide-by-4 architecture.
The required duty cycles for the time-interleaved network were generated using
gate logic. The SFDR and SNR ranges from 41dBc-34dBc and 38dB-31dB re-
spectively within the FR3 band. In stable state, the total power consumption of
the analog front-end is 484mW including the interleaving network and clock gen-
eration. This was constructed using GlobalFoundaries 22FDX technology node.
All simulations were done in Cadence Virtuoso environment. (Less)
Popular Abstract
All modern mobile phones and other electronic equipment that utilize wireless communication needs to have a receiving and transmitting architecture. These architectures are built on many different components that together makes wireless communication possible. As the speed of the communication increases with newer standards, as with 5G NR and the coming 6G, more reliable and speedy components have to be made.

The standards for 5G NR and 6G has enabled higher data-rate communication, this is because newer frequency bands have become commercially open for use. These newly opened frequency bands are called FR2 and FR3, which include parts of the spectrum that are called centimeter- and millimeter-wave. These frequency band are upwards of... (More)
All modern mobile phones and other electronic equipment that utilize wireless communication needs to have a receiving and transmitting architecture. These architectures are built on many different components that together makes wireless communication possible. As the speed of the communication increases with newer standards, as with 5G NR and the coming 6G, more reliable and speedy components have to be made.

The standards for 5G NR and 6G has enabled higher data-rate communication, this is because newer frequency bands have become commercially open for use. These newly opened frequency bands are called FR2 and FR3, which include parts of the spectrum that are called centimeter- and millimeter-wave. These frequency band are upwards of tens of GHz where the used modulation bands increase in bandwidth compare to older standards.

These higher frequency signals also suffer from higher isotropic path loss. Meaning that the wireless signal has a very short range before it attenuates fully. A solution to this is to implement a technique called beamforming. The technique builds on several antenna modules working in unison to increase directivity and therefore gain.

Once the signal has been received by the beamforming antenna modules, it is directed to the receiving architecture. Older receiving architectures utilize a technique called down-mixing. This builds on converting higher frequency signals to a more manageable frequency. The state of the art research points to a new architecture called direct RF sampling. Older architectures include several stages to the analog front-end. With direct RF sampling, this front-end can be replaced by one larger network, which grants higher flexibility and supposedly lower power consumption.

In both architectures the end stage converts the analog RF signal to a digital representation. That conversion is done with the help of an analog-to-digital converter (ADC). The peak frequency that can be accurately converted to a digital representation is limited by the sample rate of the ADC. Higher sample rate ADC gives the possibility for higher input frequency signals to be converted. It is not possible to do conversion in the intended FR3 range using one single ADC, due to its limited sample rate. Thus to achieve the required sample rate for FR3 conversion many ADCs working in parallel is needed. Each ADC receives a designated time-slot in which it alone is able to do a sample of the signal. In the next stage, on the digital side, all samples are combined to create the completed digital representation.

This Master's thesis will investigate the construction and implementation of a direct RF sampling architecture. This will be done in the technical transistor node of GlobalFoundaries 22FDX. Different design choices have been made and at the end of the thesis a complete analog front-end will be presented. (Less)
Please use this url to cite or link to this publication:
author
Callmar, Theodor LU and Andréasson, Olof
supervisor
organization
alternative title
Analogt ingångssteg för direkt RF-samplande ADC för 6G
course
EITM01 20261
year
type
H2 - Master's Degree (Two Years)
subject
keywords
6G, FR3, Time-interleaved, ADC, Clock-generation
report number
LU/LTH-EIT 2026-1173
language
English
id
9241426
date added to LUP
2026-07-01 15:21:53
date last changed
2026-07-01 15:21:53
@misc{9241426,
  abstract     = {{A time-interleaved ADC analog front-end is presented with a sampling rate of
64GS/s. It has a hierarchical architecture of 2-4-4 giving 32 separate channels.
Each channel is constructed by an input buffer, 1st rank (T/H), sub-buffer, and 2nd
rank T/H. The complimentary clocking generation consist of a 32GHz differential
signal divided down using a CML divide-by-4 and DFF divide-by-4 architecture.
The required duty cycles for the time-interleaved network were generated using
gate logic. The SFDR and SNR ranges from 41dBc-34dBc and 38dB-31dB re-
spectively within the FR3 band. In stable state, the total power consumption of
the analog front-end is 484mW including the interleaving network and clock gen-
eration. This was constructed using GlobalFoundaries 22FDX technology node.
All simulations were done in Cadence Virtuoso environment.}},
  author       = {{Callmar, Theodor and Andréasson, Olof}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Direct RF sampling ADC analog front-end for 6G}},
  year         = {{2026}},
}