Department of Electrical and Information Technology
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- 2016
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Mark
Design of a Memory Compiler
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- Master (Two yrs)
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Effect of active load on III-V NWFET Double-Balanced Gilbert Cells
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- Master (Two yrs)
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Mark
Commissioning and Characterization of Two Undulators at the MAX IV 3 GeV Storage Ring
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- Master (Two yrs)
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Mark
Prototype for Measurement Tools for Evaluating the Crusher Feed using Digital Signal Processing
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- Master (Two yrs)
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Mark
TEM Cell design for Material Characterization
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- Master (Two yrs)
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Mark
Ray-tracing based analysis of channel characteristics and capacity improvement capabilities of spatial multiplexing and beamforming at 15 and 28 GHz
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- Master (Two yrs)
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Mark
Turbo Decoder with early stopping criteria
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- Master (Two yrs)
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Mark
Modeling and Implementation of A 6-Bit, 50MHz Pipelined ADC in CMOS
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- Master (Two yrs)
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Mark
The Design and Linearization of 60GHz Injection Locked Power Amplifier
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- Master (Two yrs)
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Mark
Studies of vacuum discharges in the CLIC accelerating structure
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- Master (Two yrs)