Design of a 30 GHz PLL for use in Phased Arrays
(2016) EITM02 20161Department of Electrical and Information Technology
- Abstract
- This project includes the research and implementation of a high frequency
phase-locked loop (30 GHz or more) for beamforming use in a phased
antenna array. The phase-locked loop includes a quadrature voltagecontrolled oscillator with a 10% tuning range and 417 degrees of phase
control with a 10 degree resolution, a current mode latch in the divide-bytwo configuration operates over the quadrature voltage-controlled
oscillator’s tuning range while consuming less than 583 uA of current, Dtype flip flops in a divide-by-8 configuration, a phase-frequency detector, a
charge-pump, and a loop filter. The quadrature voltage-controlled oscillator
has a phase noise of -102.2 dBc/Hz at 1 MHz, less than 3.53 mA current
consumption, and up to... (More) - This project includes the research and implementation of a high frequency
phase-locked loop (30 GHz or more) for beamforming use in a phased
antenna array. The phase-locked loop includes a quadrature voltagecontrolled oscillator with a 10% tuning range and 417 degrees of phase
control with a 10 degree resolution, a current mode latch in the divide-bytwo configuration operates over the quadrature voltage-controlled
oscillator’s tuning range while consuming less than 583 uA of current, Dtype flip flops in a divide-by-8 configuration, a phase-frequency detector, a
charge-pump, and a loop filter. The quadrature voltage-controlled oscillator
has a phase noise of -102.2 dBc/Hz at 1 MHz, less than 3.53 mA current
consumption, and up to 185.6 dBc/Hz figure of merit. Additionally, an
injection-locked frequency divider was explored as an optional first-stage
divider. The phase-locked loop was implemented using the ST
Microelectronics 65 nanometer design kit and simulated using Cadence
Virtuoso. The circuit consumes 4.93 mA of current from a 1.2 V supply.
Lastly, the bottlenecks that may be encountered while increasing the
operating frequency of the phase-locked loop are discussed. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/8879173
- author
- Murphy, Byron LU
- supervisor
- organization
- course
- EITM02 20161
- year
- 2016
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- pll, phase-locked loop, beamforming, vco, qvco
- report number
- LU/LTH-EIT 2016-508
- language
- English
- id
- 8879173
- date added to LUP
- 2016-06-14 09:51:10
- date last changed
- 2016-06-14 09:51:10
@misc{8879173, abstract = {{This project includes the research and implementation of a high frequency phase-locked loop (30 GHz or more) for beamforming use in a phased antenna array. The phase-locked loop includes a quadrature voltagecontrolled oscillator with a 10% tuning range and 417 degrees of phase control with a 10 degree resolution, a current mode latch in the divide-bytwo configuration operates over the quadrature voltage-controlled oscillator’s tuning range while consuming less than 583 uA of current, Dtype flip flops in a divide-by-8 configuration, a phase-frequency detector, a charge-pump, and a loop filter. The quadrature voltage-controlled oscillator has a phase noise of -102.2 dBc/Hz at 1 MHz, less than 3.53 mA current consumption, and up to 185.6 dBc/Hz figure of merit. Additionally, an injection-locked frequency divider was explored as an optional first-stage divider. The phase-locked loop was implemented using the ST Microelectronics 65 nanometer design kit and simulated using Cadence Virtuoso. The circuit consumes 4.93 mA of current from a 1.2 V supply. Lastly, the bottlenecks that may be encountered while increasing the operating frequency of the phase-locked loop are discussed.}}, author = {{Murphy, Byron}}, language = {{eng}}, note = {{Student Paper}}, title = {{Design of a 30 GHz PLL for use in Phased Arrays}}, year = {{2016}}, }