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- 2023
-
Mark
A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC
(
- Master (Two yrs)
- 2020
-
Mark
PLL for 5G mmWave
(
- Master (Two yrs)
- 2016
-
Mark
Design of a 30 GHz PLL for use in Phased Arrays
(
- Master (Two yrs)
-
Mark
Prototype for Measurement Tools for Evaluating the Crusher Feed using Digital Signal Processing
(
- Master (Two yrs)
- 2015
-
Mark
DLL Based Reference Multiplier for the use in a PLL for WLAN applications
(
- Master (Two yrs)