Python-based Trace and Debug of FPGA Designs

Abstract

In the hardware development space, field programmable gate arrays (FPGAs) are
in a unique position as a result of their in-field re-programmability. In contrast
to the traditional design process of integrated circuits, FPGAs allow iterative de-
velopment workflows closely resembling software development’s sprint-based pro-
totyping. For this to work, efficient workflows for verification are key. Verification
can be done through simulators, but for complex designs with intricate depen-
dencies of surrounding hardware, these are not always sufficient. For such cases,
in-circuit debugging solutions can be utilized. These represent debugging cores
that are implemented on the FPGA silicon itself, capable of monitoring internal
signals during system runtime.
In this master’s thesis project, a debugging system has been developed. It
was designed to provide a convenient and resource efficient way to perform post-
implementation in-circuit verification of FPGA designs. The debugging system
was made to be configurable and controlled through a Python library, allowing
extensive scripting and unit-testing capabilities. The debugging system is ven-
dor and platform agnostic and easy to integrate into a pre-existing Python-based
verification workflow. We evaluated our system by comparing metrics such as ease-
of-use, functionality, and resource consumption against Xilinx Vivado’s Integrated
Logic Analyzer (ILA).

Popular Abstract

When building integrated circuits, it is important to have systems in place for
making sure that they work as intended. For this purpose, there exists computer
programs called simulators that can mimic the functionality of the circuit and show
how the internal signals react when exposed to different stimulus. Simulators are
very convenient to work with, controlled through intuitive user interfaces and gives
complete system observability. All problems cannot be solved through simulators
however, a tester needs to be able to see how the circuit behaves in the real world
and how it interacts with the hardware that it is connected to. One way to do this
is to install a so called embedded logic analyzer (ELA) inside the circuit itself. An
ELA can be seen as an advanced multimeter, it represents dedicated verification
hardware capable of monitoring signals inside the circuit. To some extent, the
goal of an ELA is to provide the functionality of a simulator but working on the
real implemented system rather than a software model.
This project is about implementing a custom ELA module written in the hard-
ware description language System Verilog. It is meant to be used for verifying a
type of programmable circuit board called FPGAs. There already exists commer-
cially available ELAs today, but the system that we have developed has a few
key features that distinguish it from these. Firstly, it is built to be completely
controlled and configured through the Python programming language. By wrap-
ping complex verification systems behind a user friendly Python library we aim to
create a streamlined verification process. Secondly, it is extensively reconfigurable
to fit a tester’s needs. Our design has systems in place for dynamically specifying
things such as which signals to monitor even after the circuit is fully constructed
and in operation. For popular commercial ELA solutions such as Xilinx Vivado’s
Integrated Logic Analyzer (ILA), these types of configurations usually have to be
done before they are built and placed in the FPGA circuit.
We have evaluated our test system against Vivado’s ILA in terms of metrics
such as how complex and resource intensive the systems are and how easy they
are to interact with for a tester. We found that our system presents some key
benefits, but also noteworthy drawbacks. On the one hand, our system proved to
be more resource efficient than Vivado’s ILA in many circumstances, in part due
to the dynamic reconfiguration feature allowing a tester to cover a large amount
of signals cheaply. On the other hand, Vivado’s ILA offers a greater breadth of
features as well as a more intuitive user interface.

• author: Sjödin, Hugo and Stenroos, Jonathan
• supervisor: Liang Liu; Lina Tinnerberg; Dumitra Iancu
• organization: Department of Electrical and Information Technology
• course: EITM01 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: FPGA, debugging, Python
• report number: LU/LTH-EIT 2026-1118
• language: English
• id: 9225905
• date added to LUP: 2026-06-04 15:28:06
• date last changed: 2026-06-04 15:28:06