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- 2019
-
Mark
BIST Implementation Access through A Reconfigurable Network
(
- Master (Two yrs)
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Mark
Investigate Redundancy In Sounding Reference Signal Based Channel Estimates
(
- Master (Two yrs)
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Mark
Design of High Speed in Memory Serializer/Deserializer with Integrated Sense Amplifier
(
- Master (Two yrs)
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Mark
DSP Design With Hardware Accelerator For Convolutional Neural Networks
(
- Master (Two yrs)
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Mark
Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
(
- Master (Two yrs)
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Mark
Reconfigurable Instrument Access Network with a Functional Port Interface
(
- Master (Two yrs)
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Mark
Beamforming Solutions for Efficient Link Setup and Link Maintenance in mmWave Communication Systems
(
- Master (Two yrs)
-
Mark
Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint
(
- Master (Two yrs)
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Mark
Machine Learning Technique for Uplink Link Adaptation in 5G NR RAN at Millimeter Wave Frequencies
(
- Master (Two yrs)
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Mark
Spatially Coupled Codes in Turbo Equalization
(
- Master (Two yrs)