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- 2024
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Mark
Voltage Threshold Optimization: Balancing Leakage and Performance in Integrated Circuits
(
- Master (Two yrs)
- 2020
-
Mark
Design of Two 28 GHz Doherty Power Amplifier Topologies with Vertical In(Ga)As Nanowire Transistors
(
- Master (Two yrs)
- 2017
-
Mark
Fabrication and Charaterisation of Finger Gates
(
- Master (Two yrs)
-
Mark
GaSb nanowire transistors with process induced strain
(
- Master (Two yrs)
- 2016
-
Mark
Vertical heterostructure III-V nanowire MOSFETs
2016) In Vertical heterostructure III-V nanowire MOSFETs EITM01 20161(
Department of Electrical and Information Technology- Master (Two yrs)
- 2009
-
Mark
Automated modelling and optimization of a ratioed logic inverter utilizing nanowire-based transistors
(
- Master (Two yrs)