A 3-level asynchronous protocol for a differential two-wire communication link
(1994) In IEEE Journal of Solid-State Circuits 29(9). p.1129-1132- Abstract
- A differential two-wire communication link with a 3-level asynchronous protocol is introduced. The proposed 3-level code contains information of both data and clock. Since only one edge is needed for each bit, the bandwidth of a link is efficiently utilized. The power consumption is reduced by the low-swing differential two-wire link and is further reduced by a 3-level code. The speed of the protocol is expected to reach 1 Gb/s in a 1.2-μm CMOS process.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1748960
- author
- Svensson, Christer and Yuan, Jiren LU
- publishing date
- 1994
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- CMOS integrated circuits, clocks, decoding, digital communication systems, digital integrated circuits, encoding, protocols, pulse-code modulation links, telecommunication links
- in
- IEEE Journal of Solid-State Circuits
- volume
- 29
- issue
- 9
- pages
- 1129 - 1132
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:0028495283
- ISSN
- 0018-9200
- DOI
- 10.1109/4.309909
- language
- English
- LU publication?
- no
- id
- 685d04c9-aac7-441e-aaec-7306a590c703 (old id 1748960)
- date added to LUP
- 2016-04-04 09:05:13
- date last changed
- 2021-01-03 08:35:13
@article{685d04c9-aac7-441e-aaec-7306a590c703, abstract = {{A differential two-wire communication link with a 3-level asynchronous protocol is introduced. The proposed 3-level code contains information of both data and clock. Since only one edge is needed for each bit, the bandwidth of a link is efficiently utilized. The power consumption is reduced by the low-swing differential two-wire link and is further reduced by a 3-level code. The speed of the protocol is expected to reach 1 Gb/s in a 1.2-μm CMOS process.}}, author = {{Svensson, Christer and Yuan, Jiren}}, issn = {{0018-9200}}, keywords = {{CMOS integrated circuits; clocks; decoding; digital communication systems; digital integrated circuits; encoding; protocols; pulse-code modulation links; telecommunication links}}, language = {{eng}}, number = {{9}}, pages = {{1129--1132}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Journal of Solid-State Circuits}}, title = {{A 3-level asynchronous protocol for a differential two-wire communication link}}, url = {{http://dx.doi.org/10.1109/4.309909}}, doi = {{10.1109/4.309909}}, volume = {{29}}, year = {{1994}}, }