Scheduling Tests for Stacked 3D Chips under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2010)
Swedish SoC Conference 2010
- Abstract
- This paper addresses test application time (TAT)
reduction for core-based stacked 3D chips. In contrast to the
traditional method of testing non-stacked chips where the same
test schedule is applied both at wafer test and at final test, stacked
3D chips need a pre-bond test schedule for each individual chip
and a different post-bond test schedule where all chips are jointly
tested. We consider a system of core-based chips where each core
is tested with a dedicated Built-In Self-Test (BIST) engine and
define an algorithm that defines each pre-bond test schedule and
the post-bond test schedule such that the overall TAT is
minimized and power constraints... (More) - This paper addresses test application time (TAT)
reduction for core-based stacked 3D chips. In contrast to the
traditional method of testing non-stacked chips where the same
test schedule is applied both at wafer test and at final test, stacked
3D chips need a pre-bond test schedule for each individual chip
and a different post-bond test schedule where all chips are jointly
tested. We consider a system of core-based chips where each core
is tested with a dedicated Built-In Self-Test (BIST) engine and
define an algorithm that defines each pre-bond test schedule and
the post-bond test schedule such that the overall TAT is
minimized and power constraints are met. The cost due to the
number of BIST control-lines is also taken into account.
Experiments with the proposed algorithm show significant savings
in TAT. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340861
- author
- Sengupta, Breeta
LU
; Ingelsson, Urban
and Larsson, Erik
LU
- organization
- publishing date
- 2010
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- Built in Self Test (BIST), Design for Test (DfT), Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV).
- pages
- 4 pages
- conference name
- Swedish SoC Conference 2010
- conference location
- Kolmården, Sweden
- conference dates
- 2010-05-03 - 2010-05-04
- language
- English
- LU publication?
- no
- id
- c72c0c53-7ade-48e6-af6d-9bdab442c8a0 (old id 2340861)
- date added to LUP
- 2016-04-04 14:39:18
- date last changed
- 2020-06-10 15:44:17
@misc{c72c0c53-7ade-48e6-af6d-9bdab442c8a0,
abstract = {{This paper addresses test application time (TAT)<br/><br>
reduction for core-based stacked 3D chips. In contrast to the<br/><br>
traditional method of testing non-stacked chips where the same<br/><br>
test schedule is applied both at wafer test and at final test, stacked<br/><br>
3D chips need a pre-bond test schedule for each individual chip<br/><br>
and a different post-bond test schedule where all chips are jointly<br/><br>
tested. We consider a system of core-based chips where each core<br/><br>
is tested with a dedicated Built-In Self-Test (BIST) engine and<br/><br>
define an algorithm that defines each pre-bond test schedule and<br/><br>
the post-bond test schedule such that the overall TAT is<br/><br>
minimized and power constraints are met. The cost due to the<br/><br>
number of BIST control-lines is also taken into account.<br/><br>
Experiments with the proposed algorithm show significant savings<br/><br>
in TAT.}},
author = {{Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik}},
keywords = {{Built in Self Test (BIST); Design for Test (DfT); Test scheduling; Sessions; Test time; Test cost; 3D Stacked Integrated Circuit (SIC); Through Silicon Via (TSV).}},
language = {{eng}},
title = {{Scheduling Tests for Stacked 3D Chips under Power Constraints}},
url = {{https://lup.lub.lu.se/search/files/6409896/4857403.pdf}},
year = {{2010}},
}