A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
(2011) IEEE European Solid State Circuits Conference, ESSCIRC 2011 p.459-462- Abstract
- Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2437163
- author
- Lu, Ping LU ; Andreani, Pietro LU and Liscidini, Antonio
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Time-to-Digital Converter, Gated Ring Oscillator, Vernier Delay Line
- host publication
- [Host publication title missing]
- pages
- 459 - 462
- conference name
- IEEE European Solid State Circuits Conference, ESSCIRC 2011
- conference location
- Helsinki, Finland
- conference dates
- 2011-09-12 - 2011-09-16
- external identifiers
-
- scopus:82955213931
- ISSN
- 1930-8833
- ISBN
- 978-1-4577-0703-2
- DOI
- 10.1109/ESSCIRC.2011.6045006
- language
- English
- LU publication?
- yes
- id
- 9fc6a540-1c5c-4f82-8ff8-40ca517babbc (old id 2437163)
- date added to LUP
- 2016-04-04 09:07:33
- date last changed
- 2022-03-15 17:48:35
@inproceedings{9fc6a540-1c5c-4f82-8ff8-40ca517babbc, abstract = {{Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.}}, author = {{Lu, Ping and Andreani, Pietro and Liscidini, Antonio}}, booktitle = {{[Host publication title missing]}}, isbn = {{978-1-4577-0703-2}}, issn = {{1930-8833}}, keywords = {{Time-to-Digital Converter; Gated Ring Oscillator; Vernier Delay Line}}, language = {{eng}}, pages = {{459--462}}, title = {{A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution}}, url = {{http://dx.doi.org/10.1109/ESSCIRC.2011.6045006}}, doi = {{10.1109/ESSCIRC.2011.6045006}}, year = {{2011}}, }