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Partitioning and Mapping Dynamic Dataflow Programs

Arslan, Mehmet Ali LU ; Janneck, Jörn LU and Kuchcinski, Krzysztof LU orcid (2012) 46th Annual Asilomar Conference on Signals, Systems, and Computers, 2012 p.1452-1456
Abstract
Partitioning and mapping are important design decisions in exploiting the parallelism of programs that are to be run on systems with multiple processing elements. In this paper we introduce a fast, incremental approach for mapping dynamic dataflow programs to multiprocessor systems. We use causation traces and architecture descriptions as input for the mapping process that devises several heuristics for reaching a short makespan for the given trace. We evaluate our approach by comparing our results to two different lower bounds and another algorithm used often in solving mapping problems: simulated annealing.
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
partitioning, mapping, scheduling, dataflow, traces
host publication
[Host publication title missing]
pages
5 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
46th Annual Asilomar Conference on Signals, Systems, and Computers, 2012
conference location
Pacific Grove, California, United States
conference dates
2012-11-04 - 2012-11-07
external identifiers
  • wos:000320768400269
  • scopus:84876254233
ISSN
1058-6393
project
High Performance Embedded Computing
language
English
LU publication?
yes
id
e965784c-f974-422b-baa4-1097299e9efa (old id 3210059)
date added to LUP
2016-04-01 13:35:07
date last changed
2022-05-15 06:02:37
@inproceedings{e965784c-f974-422b-baa4-1097299e9efa,
  abstract     = {{Partitioning and mapping are important design decisions in exploiting the parallelism of programs that are to be run on systems with multiple processing elements. In this paper we introduce a fast, incremental approach for mapping dynamic dataflow programs to multiprocessor systems. We use causation traces and architecture descriptions as input for the mapping process that devises several heuristics for reaching a short makespan for the given trace. We evaluate our approach by comparing our results to two different lower bounds and another algorithm used often in solving mapping problems: simulated annealing.}},
  author       = {{Arslan, Mehmet Ali and Janneck, Jörn and Kuchcinski, Krzysztof}},
  booktitle    = {{[Host publication title missing]}},
  issn         = {{1058-6393}},
  keywords     = {{partitioning; mapping; scheduling; dataflow; traces}},
  language     = {{eng}},
  pages        = {{1452--1456}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Partitioning and Mapping Dynamic Dataflow Programs}},
  year         = {{2012}},
}