Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs
(2015) 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015 p.61-64- Abstract
We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kane's tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/33ff9308-0f41-48c7-bf84-9ae3d38a7f2f
- author
- Cutaia, Davide ; Moselund, Kirsten E. ; Borg, M. LU ; Schmid, Heinz ; Gignac, L. ; Breslin, C. M. ; Karg, Siegfried ; Uccelli, Emanuele ; Nirmalraj, P. and Riel, Heike
- publishing date
- 2015-03-18
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- hetero-junctions, IH-V semiconductor materials, Kane model, low-power electronics, nanowires, tunnel transistor
- host publication
- EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
- article number
- 7063773
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015
- conference location
- Bologna, Italy
- conference dates
- 2015-01-26 - 2015-01-28
- external identifiers
-
- scopus:84926429672
- ISBN
- 9781479969111
- DOI
- 10.1109/ULIS.2015.7063773
- language
- English
- LU publication?
- no
- id
- 33ff9308-0f41-48c7-bf84-9ae3d38a7f2f
- date added to LUP
- 2017-03-02 13:59:28
- date last changed
- 2022-03-16 20:49:42
@inproceedings{33ff9308-0f41-48c7-bf84-9ae3d38a7f2f, abstract = {{<p>We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kane's tunneling model for direct bandgap (E<sub>g</sub>) materials and compare it with experimental results. Moreover, studying the activation energy (E<sub>A</sub>) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.</p>}}, author = {{Cutaia, Davide and Moselund, Kirsten E. and Borg, M. and Schmid, Heinz and Gignac, L. and Breslin, C. M. and Karg, Siegfried and Uccelli, Emanuele and Nirmalraj, P. and Riel, Heike}}, booktitle = {{EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon}}, isbn = {{9781479969111}}, keywords = {{hetero-junctions; IH-V semiconductor materials; Kane model; low-power electronics; nanowires; tunnel transistor}}, language = {{eng}}, month = {{03}}, pages = {{61--64}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs}}, url = {{http://dx.doi.org/10.1109/ULIS.2015.7063773}}, doi = {{10.1109/ULIS.2015.7063773}}, year = {{2015}}, }