A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems
(2015) In International Journal of Circuit Theory and Applications 43(4). p.489-501- Abstract
- A 128-channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65-nm complementary metal-oxide semiconductor process. The post-layout simulated power consumption at 1.2 V is 33.06 μW (258 nW per channel) at an area cost of 0.46 mm2
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4076724
- author
- Hosseini-Nejad, Hossein ; Jannesari, Abumoslem ; Sodagar, Amir and Rodrigues, Joachim LU
- organization
- publishing date
- 2015
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Neural processsing, data compression, ASIC, low power
- in
- International Journal of Circuit Theory and Applications
- volume
- 43
- issue
- 4
- pages
- 489 - 501
- publisher
- John Wiley & Sons Inc.
- external identifiers
-
- wos:000353639900007
- scopus:84927698712
- ISSN
- 1097-007X
- DOI
- 10.1002/cta.1955
- language
- English
- LU publication?
- yes
- id
- 810adf78-0747-4885-908e-219a7f97aed3 (old id 4076724)
- date added to LUP
- 2016-04-01 10:42:39
- date last changed
- 2022-03-12 08:22:14
@article{810adf78-0747-4885-908e-219a7f97aed3, abstract = {{A 128-channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65-nm complementary metal-oxide semiconductor process. The post-layout simulated power consumption at 1.2 V is 33.06 μW (258 nW per channel) at an area cost of 0.46 mm2}}, author = {{Hosseini-Nejad, Hossein and Jannesari, Abumoslem and Sodagar, Amir and Rodrigues, Joachim}}, issn = {{1097-007X}}, keywords = {{Neural processsing; data compression; ASIC; low power}}, language = {{eng}}, number = {{4}}, pages = {{489--501}}, publisher = {{John Wiley & Sons Inc.}}, series = {{International Journal of Circuit Theory and Applications}}, title = {{A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems}}, url = {{http://dx.doi.org/10.1002/cta.1955}}, doi = {{10.1002/cta.1955}}, volume = {{43}}, year = {{2015}}, }