Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration
(2013) NORCHIP Conference, 2013- Abstract
- This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4144312
- author
- Granlund, Stefan ; Liu, Liang LU ; Zhang, Chenxin LU and Öwall, Viktor LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 4 pages
- conference name
- NORCHIP Conference, 2013
- conference location
- Vilnius, Lithuania
- conference dates
- 2013-11-11 - 2013-11-12
- external identifiers
-
- scopus:84893569129
- DOI
- 10.1109/NORCHIP.2013.6702034
- project
- High Performance Embedded Computing
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- id
- b22d1b7d-20c5-48a3-ae5d-ff521798ce1c (old id 4144312)
- alternative location
- http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6702034&tag=1
- date added to LUP
- 2016-04-04 13:46:44
- date last changed
- 2024-01-13 09:21:52
@inproceedings{b22d1b7d-20c5-48a3-ae5d-ff521798ce1c, abstract = {{This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.}}, author = {{Granlund, Stefan and Liu, Liang and Zhang, Chenxin and Öwall, Viktor}}, booktitle = {{[Host publication title missing]}}, language = {{eng}}, title = {{Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration}}, url = {{http://dx.doi.org/10.1109/NORCHIP.2013.6702034}}, doi = {{10.1109/NORCHIP.2013.6702034}}, year = {{2013}}, }