III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon
(2016) 11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016- Abstract
In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = -0.5V, combined with average subthreshold swings (SS) of 70-80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The... (More)
In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = -0.5V, combined with average subthreshold swings (SS) of 70-80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The InAs/GaSb n-TFETs represent our first devices in this material system, with doping levels and gate stack not yet optimized; the all III-V TFETs show about an order of magnitude greater current levels, but at a worse SS.
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- author
- Moselund, Kirsten E. ; Cutaia, Davide ; Schmid, Heinz ; Borg, M. LU ; Sant, Saurabh ; Schenk, Andreas and Riel, Heike
- organization
- publishing date
- 2016-12-07
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Nanotechnology Materials and Devices Conference, NMDC 2016 - Conference Proceedings
- article number
- 7777149
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016
- conference location
- Toulouse, France
- conference dates
- 2016-10-09 - 2016-10-12
- external identifiers
-
- scopus:85010424669
- ISBN
- 9781509043521
- DOI
- 10.1109/NMDC.2016.7777149
- language
- English
- LU publication?
- no
- id
- 5922a15f-cb61-4edc-8db4-aaf86a0ab39f
- date added to LUP
- 2017-03-02 13:57:13
- date last changed
- 2023-10-05 00:46:55
@inproceedings{5922a15f-cb61-4edc-8db4-aaf86a0ab39f, abstract = {{<p>In this presentation we will discuss our recent progress on the integration of InAs/Si p-tunnel FETs (TFETs) and InAs/GaSb n-TFETs on SOI wafers. Local III-V growth is enabled by the development of Template-Assisted Selective Epitaxy (TASE) [1-4]. Both polarity devices have scaled geometries with cross-sections on the order of 30nm. The p-channel InAs/Si TFETs are developed based on our previously demonstrated vertical devices, which are now implemented horizontally in-plane on the Si wafer. The InAs/Si TFETs show excellent performance with Ion of about 4μA/μm at Vgs = Vds = -0.5V, combined with average subthreshold swings (SS) of 70-80mV/dec. The SS is limited by trap mechanisms at the heterojunction, which will also be discussed. The InAs/GaSb n-TFETs represent our first devices in this material system, with doping levels and gate stack not yet optimized; the all III-V TFETs show about an order of magnitude greater current levels, but at a worse SS.</p>}}, author = {{Moselund, Kirsten E. and Cutaia, Davide and Schmid, Heinz and Borg, M. and Sant, Saurabh and Schenk, Andreas and Riel, Heike}}, booktitle = {{Nanotechnology Materials and Devices Conference, NMDC 2016 - Conference Proceedings}}, isbn = {{9781509043521}}, language = {{eng}}, month = {{12}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon}}, url = {{http://dx.doi.org/10.1109/NMDC.2016.7777149}}, doi = {{10.1109/NMDC.2016.7777149}}, year = {{2016}}, }