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- 2019
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Mark
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy
(
- Contribution to journal › Article
- 2018
-
Mark
Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs
2018) In Composants nanoélectroniques(
- Contribution to journal › Article
- 2017
-
Mark
Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade
2017) In Nano Letters(
- Contribution to journal › Letter
- 2016
-
Mark
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 1 : Experimental Devices
(
- Contribution to journal › Article
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Mark
III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon
2016) 11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2 : Simulation Study of the Impact of Interface Traps
(
- Contribution to journal › Article