Lars-Erik Wernersson
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- 2019
- An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
- Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
- Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
- 2018
- Clutter analysis in a time-domain millimeter-wave reflectometry setup
- Fabrication of Tunnel Field-Effect Transistors
- Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
- CMOS Integration Based on All-III-V Materials
- Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire Tunnel Field-Effect Transistors
- Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
- A Self-aligned Gate-last Process applied to All-III-V CMOS on Si