Lars-Erik Wernersson
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- 2021
-
Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation
Andric, Stefan LU ; Ohlsson-Fhager, Lars LU
and Wernersson, Lars Erik
LU
(2021)
15th European Microwave Integrated Circuits Conference, EuMIC 2020
In EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference
p.85-88
Mark
-
Tuning oxygen vacancies and resistive switching properties in ultra-thin HfO2 RRAM via TiN bottom electrode and interface engineering
Yong, Zhihua LU ; Persson, Karl-Magnus LU ; Mamidala, Saketh, Ram LU
; D Acunto, Giulio
LU
; Liu, Yi
LU
; Benter, Sandra
LU
; Pan, Jisheng
; Li, Zheshen
; Borg, Mattias
LU
and Mikkelsen, Anders
LU
, et al.
(2021)
In Applied Surface Science
551.
Mark
- 2020
-
A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
Heunisch, Sebastian LU ; Ohlsson Fhager, Lars LU
and Wernersson, Lars Erik
LU
(2020)
In International Journal of Circuit Theory and Applications
48(1).
p.103-114
Mark
-
Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
Mamidala, Saketh, Ram LU
; Persson, Karl-Magnus
LU
; Borg, Mattias
LU
and Wernersson, Lars-Erik
LU
(2020)
In IEEE Electron Device Letters
41(9).
p.1432-1435
Mark
- Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
-
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
Dzhigaev, Dmitry LU
; Svensson, Johannes
LU
; Krishnaraja, Abinaya
LU
; Zhu, Zhongyunshen
LU
; Ren, Zhe
LU
; Liu, Yi
LU
; Kalbfleisch, Sebastian
LU
; Björling, Alexander
LU
; Lenrick, Filip
LU
and Balogh, Zoltan Imre
, et al.
(2020)
In Nanoscale
12(27).
p.14487-14493
Mark
- Reduced annealing temperature for ferroelectric HZO on InAs with enhanced polarization
-
Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
Persson, Karl-Magnus LU ; Mamidala, Saketh, Ram LU
; Kilpi, Olli-Pekka
LU
; Borg, Mattias
LU
and Wernersson, Lars-Erik
LU
(2020)
In Advanced Electronic Materials
6(6).
Mark
- Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
- Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs