Advanced

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Sant, Saurabh; Memisevic, Elvedin LU ; Wernersson, Lars-Erik LU and Schenk, Andreas (2018) In Composants nanoélectroniques
Abstract
Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate... (More)
Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Composants nanoélectroniques
ISSN
2516-3914
DOI
10.21494/ISTE.OP.2018.0221
language
English
LU publication?
yes
id
8d44e46a-65ad-4785-b8c4-972bdcd1129e
date added to LUP
2018-07-05 11:33:38
date last changed
2018-11-21 21:40:39
@article{8d44e46a-65ad-4785-b8c4-972bdcd1129e,
  abstract     = {Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found. },
  author       = {Sant, Saurabh and Memisevic, Elvedin and Wernersson, Lars-Erik and Schenk, Andreas},
  issn         = {2516-3914},
  language     = {eng},
  series       = {Composants nanoélectroniques},
  title        = {Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs},
  url          = {http://dx.doi.org/10.21494/ISTE.OP.2018.0221},
  year         = {2018},
}