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Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2 : Simulation Study of the Impact of Interface Traps

Sant, Saurabh; Moselund, Kirsten E.; Cutaia, Davide; Schmid, Heinz; Borg, Mattias LU ; Riel, Heike and Schenk, Andreas (2016) In IEEE Transactions on Electron Devices 63(11). p.4240-4247
Abstract

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at... (More)

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a subthermal SS would only be achievable for Dit < 5× 1011 cm-2 eV-1 at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of Dit < 1× 1012 cm-2 eV-1 for vertical InAs/Si NW TFETs with larger diameters.

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author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
InAs/oxide interface, InAs/Si interface, interface traps, tunnel FETs (TFETs)
in
IEEE Transactions on Electron Devices
volume
63
issue
11
pages
8 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:84994005784
ISSN
0018-9383
DOI
10.1109/TED.2016.2612484
language
English
LU publication?
no
id
fee0a1dd-40ba-47d5-b5e5-1ec7685eddd3
date added to LUP
2017-03-02 13:57:55
date last changed
2017-10-29 04:58:59
@article{fee0a1dd-40ba-47d5-b5e5-1ec7685eddd3,
  abstract     = {<p>This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a subthermal SS would only be achievable for D<sub>it</sub> &lt; 5× 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup> at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of D<sub>it</sub> &lt; 1× 10<sup>12</sup> cm<sup>-2</sup> eV<sup>-1</sup> for vertical InAs/Si NW TFETs with larger diameters.</p>},
  articleno    = {7582481},
  author       = {Sant, Saurabh and Moselund, Kirsten E. and Cutaia, Davide and Schmid, Heinz and Borg, Mattias and Riel, Heike and Schenk, Andreas},
  issn         = {0018-9383},
  keyword      = {InAs/oxide interface,InAs/Si interface,interface traps,tunnel FETs (TFETs)},
  language     = {eng},
  month        = {11},
  number       = {11},
  pages        = {4240--4247},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Electron Devices},
  title        = {Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2 : Simulation Study of the Impact of Interface Traps},
  url          = {http://dx.doi.org/10.1109/TED.2016.2612484},
  volume       = {63},
  year         = {2016},
}