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Trap-aware compact modeling and power-performance assessment of III-V tunnel FET

Xiang, Yang; Yakimets, Dmitry; Sant, Saurabh; Memisevic, Elvedin LU ; Bardon, Marie Garcia; Verhulst, Anne S.; Parvais, Bertrand; Schenk, Andreas; Wernersson, Lars Erik LU and Groeseneken, Guido (2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Abstract

We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ∼5x iso-frequency energy... (More)

We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ∼5x iso-frequency energy penalty in the desired low-supply-voltage domain (0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.

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Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Compact modeling, Device traps, III-V tunnel FET, Logic circuits, Power-performance metrics, SPICE simulation
host publication
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
publisher
Institute of Electrical and Electronics Engineers Inc.
conference name
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
conference location
Burlingame, United States
conference dates
2018-10-15 - 2018-10-18
external identifiers
  • scopus:85063155130
ISBN
9781538676264
DOI
10.1109/S3S.2018.8640183
language
English
LU publication?
yes
id
83ac76f7-4c57-4f5e-b42a-581749267ce0
date added to LUP
2019-04-02 11:03:31
date last changed
2019-04-23 04:48:05
@inproceedings{83ac76f7-4c57-4f5e-b42a-581749267ce0,
  abstract     = {<p>We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ∼5x iso-frequency energy penalty in the desired low-supply-voltage domain (0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.</p>},
  author       = {Xiang, Yang and Yakimets, Dmitry and Sant, Saurabh and Memisevic, Elvedin and Bardon, Marie Garcia and Verhulst, Anne S. and Parvais, Bertrand and Schenk, Andreas and Wernersson, Lars Erik and Groeseneken, Guido},
  isbn         = {9781538676264},
  keyword      = {Compact modeling,Device traps,III-V tunnel FET,Logic circuits,Power-performance metrics,SPICE simulation},
  language     = {eng},
  location     = {Burlingame, United States},
  month        = {02},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  title        = {Trap-aware compact modeling and power-performance assessment of III-V tunnel FET},
  url          = {http://dx.doi.org/10.1109/S3S.2018.8640183},
  year         = {2019},
}