A digitally controlled PLL for digital SOCs
(2003) Proceedings of the 2003 IEEE International Symposium on Circuits and Systems 5. p.437-440- Abstract
- A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/612770
- author
- Olsson, Thomas LU and Nilsson, Peter LU
- organization
- publishing date
- 2003
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Digital systems
- host publication
- Proceedings - IEEE International Symposium on Circuits and Systems
- volume
- 5
- pages
- 437 - 440
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
- conference location
- Bangkok, Thailand
- conference dates
- 2003-05-25 - 2003-05-28
- external identifiers
-
- wos:000184904800110
- other:CODEN: PICSDI
- scopus:0038420044
- ISSN
- 2158-1525
- 0271-4310
- DOI
- 10.1109/ISCAS.2003.1206308
- language
- English
- LU publication?
- yes
- id
- 84479eb2-3edd-4fbb-ae7b-c23f477ea889 (old id 612770)
- date added to LUP
- 2016-04-01 12:24:07
- date last changed
- 2024-07-18 00:11:10
@inproceedings{84479eb2-3edd-4fbb-ae7b-c23f477ea889, abstract = {{A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm<sup>2</sup>. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.}}, author = {{Olsson, Thomas and Nilsson, Peter}}, booktitle = {{Proceedings - IEEE International Symposium on Circuits and Systems}}, issn = {{2158-1525}}, keywords = {{Digital systems}}, language = {{eng}}, pages = {{437--440}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A digitally controlled PLL for digital SOCs}}, url = {{http://dx.doi.org/10.1109/ISCAS.2003.1206308}}, doi = {{10.1109/ISCAS.2003.1206308}}, volume = {{5}}, year = {{2003}}, }