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A low logic depth complex multiplier

Berkeman, Anders LU ; Öwall, Viktor LU and Torkelson, Mats LU (1998) European Solid-State Circuits Conference (ESSCIRC), 1998 p.204-207
Abstract
A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
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author
organization
publishing date
type
Contribution to conference
publication status
published
subject
pages
204 - 207
conference name
European Solid-State Circuits Conference (ESSCIRC), 1998
external identifiers
  • Scopus:0347073324
language
English
LU publication?
yes
id
44d1cce2-29cc-42cd-82ad-ef73e6b1d7e4 (old id 1225670)
date added to LUP
2008-09-05 10:40:28
date last changed
2016-10-13 05:03:34
@misc{44d1cce2-29cc-42cd-82ad-ef73e6b1d7e4,
  abstract     = {A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.},
  author       = {Berkeman, Anders and Öwall, Viktor and Torkelson, Mats},
  language     = {eng},
  pages        = {204--207},
  title        = {A low logic depth complex multiplier},
  year         = {1998},
}