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Scheduling Tests for Stacked 3D Chips under Power Constraints

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2010) Swedish SoC Conference 2010
Abstract
This paper addresses test application time (TAT)

reduction for core-based stacked 3D chips. In contrast to the

traditional method of testing non-stacked chips where the same

test schedule is applied both at wafer test and at final test, stacked

3D chips need a pre-bond test schedule for each individual chip

and a different post-bond test schedule where all chips are jointly

tested. We consider a system of core-based chips where each core

is tested with a dedicated Built-In Self-Test (BIST) engine and

define an algorithm that defines each pre-bond test schedule and

the post-bond test schedule such that the overall TAT is

minimized and power constraints... (More)
This paper addresses test application time (TAT)

reduction for core-based stacked 3D chips. In contrast to the

traditional method of testing non-stacked chips where the same

test schedule is applied both at wafer test and at final test, stacked

3D chips need a pre-bond test schedule for each individual chip

and a different post-bond test schedule where all chips are jointly

tested. We consider a system of core-based chips where each core

is tested with a dedicated Built-In Self-Test (BIST) engine and

define an algorithm that defines each pre-bond test schedule and

the post-bond test schedule such that the overall TAT is

minimized and power constraints are met. The cost due to the

number of BIST control-lines is also taken into account.

Experiments with the proposed algorithm show significant savings

in TAT. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
Built in Self Test (BIST), Design for Test (DfT), Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV).
pages
4 pages
conference name
Swedish SoC Conference 2010
language
English
LU publication?
no
id
c72c0c53-7ade-48e6-af6d-9bdab442c8a0 (old id 2340861)
date added to LUP
2012-02-10 13:59:00
date last changed
2016-04-16 12:49:14
@misc{c72c0c53-7ade-48e6-af6d-9bdab442c8a0,
  abstract     = {This paper addresses test application time (TAT)<br/><br>
reduction for core-based stacked 3D chips. In contrast to the<br/><br>
traditional method of testing non-stacked chips where the same<br/><br>
test schedule is applied both at wafer test and at final test, stacked<br/><br>
3D chips need a pre-bond test schedule for each individual chip<br/><br>
and a different post-bond test schedule where all chips are jointly<br/><br>
tested. We consider a system of core-based chips where each core<br/><br>
is tested with a dedicated Built-In Self-Test (BIST) engine and<br/><br>
define an algorithm that defines each pre-bond test schedule and<br/><br>
the post-bond test schedule such that the overall TAT is<br/><br>
minimized and power constraints are met. The cost due to the<br/><br>
number of BIST control-lines is also taken into account.<br/><br>
Experiments with the proposed algorithm show significant savings<br/><br>
in TAT.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  keyword      = {Built in Self Test (BIST),Design for Test (DfT),Test scheduling,Sessions,Test time,Test cost,3D Stacked Integrated Circuit (SIC),Through Silicon Via (TSV).},
  language     = {eng},
  pages        = {4},
  title        = {Scheduling Tests for Stacked 3D Chips under Power Constraints},
  year         = {2010},
}