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Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

Granlund, Stefan; Liu, Liang LU ; Zhang, Chenxin LU and Öwall, Viktor LU (2013) NORCHIP Conference, 2013 In [Host publication title missing]
Abstract
This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
4 pages
conference name
NORCHIP Conference, 2013
external identifiers
  • Scopus:84893569129
DOI
10.1109/NORCHIP.2013.6702034
project
EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
HiPEC
language
English
LU publication?
yes
id
b22d1b7d-20c5-48a3-ae5d-ff521798ce1c (old id 4144312)
alternative location
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6702034&tag=1
date added to LUP
2013-11-07 09:14:01
date last changed
2016-10-13 04:57:31
@misc{b22d1b7d-20c5-48a3-ae5d-ff521798ce1c,
  abstract     = {This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.},
  author       = {Granlund, Stefan and Liu, Liang and Zhang, Chenxin and Öwall, Viktor},
  language     = {eng},
  pages        = {4},
  series       = {[Host publication title missing]},
  title        = {Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration},
  url          = {http://dx.doi.org/10.1109/NORCHIP.2013.6702034},
  year         = {2013},
}