Advanced

An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

Mohammadi, Babak LU ; Andersson, Oskar LU ; Luo, Xiao; Nouripayam, Masoud and Rodrigues, Joachim LU (2016) IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016 In IEEE A-SSCC (Asian Solid-State Circuits Conference) 2016
Abstract
An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise... (More)
An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
in press
subject
in
IEEE A-SSCC (Asian Solid-State Circuits Conference) 2016
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016
language
English
LU publication?
yes
id
f93ac542-e36a-4dac-bb3f-3bd91302eff2
date added to LUP
2016-08-29 16:51:56
date last changed
2016-08-30 09:18:36
@misc{f93ac542-e36a-4dac-bb3f-3bd91302eff2,
  abstract     = {An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V. },
  author       = {Mohammadi, Babak and Andersson, Oskar and Luo, Xiao and Nouripayam, Masoud and Rodrigues, Joachim},
  language     = {eng},
  publisher    = {ARRAY(0x89a7548)},
  series       = {IEEE A-SSCC (Asian Solid-State Circuits Conference) 2016},
  title        = {An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI},
  year         = {2016},
}