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An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

Mohammadi, Babak LU ; Andersson, Oskar LU ; Luo, Xiao ; Nouripayam, Masoud LU and Rodrigues, Joachim LU (2017) IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016 p.229-232
Abstract
An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise... (More)
An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V. (Less)
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author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
pages
229 - 232
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016
conference location
Toyama, Japan
conference dates
2016-11-07 - 2016-11-09
external identifiers
  • scopus:85015149443
ISBN
978-150903700-1
DOI
10.1109/ASSCC.2016.7844177
language
English
LU publication?
yes
id
f93ac542-e36a-4dac-bb3f-3bd91302eff2
date added to LUP
2016-08-29 16:51:56
date last changed
2022-04-26 10:22:24
@inproceedings{f93ac542-e36a-4dac-bb3f-3bd91302eff2,
  abstract     = {{An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V.}},
  author       = {{Mohammadi, Babak and Andersson, Oskar and Luo, Xiao and Nouripayam, Masoud and Rodrigues, Joachim}},
  booktitle    = {{2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)}},
  isbn         = {{978-150903700-1}},
  language     = {{eng}},
  pages        = {{229--232}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI}},
  url          = {{http://dx.doi.org/10.1109/ASSCC.2016.7844177}},
  doi          = {{10.1109/ASSCC.2016.7844177}},
  year         = {{2017}},
}