Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop
(2007) p.2593-2599- Abstract
- This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 ¿m BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1050968
- author
- Ayranci, Emre ; Christensen, Kenn and Andreani, Pietro LU
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- EUROCON, 2007. The International Conference on "Computer as a Tool"
- pages
- 2593 - 2599
- external identifiers
-
- scopus:46149123917
- ISBN
- 978-1-4244-0813-9
- DOI
- 10.1109/EURCON.2007.4400681
- language
- English
- LU publication?
- no
- id
- d33622c5-baa6-44fd-a390-5cd53155976d (old id 1050968)
- alternative location
- http://ieeexplore.ieee.org/iel5/4400217/4400218/04400681.pdf
- date added to LUP
- 2016-04-04 14:27:32
- date last changed
- 2022-03-16 03:26:00
@inproceedings{d33622c5-baa6-44fd-a390-5cd53155976d, abstract = {{This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases the phase noise and linearizes the transfer function. Implementation of the FLL inside a PLL is also investigated and a possible application is highlighted. Design of a special kind of low noise frequency detector without a reference frequency (frequency-to-voltage converter), which is the most critical component of the FLL, is also presented in a 0.25 ¿m BiCMOS process. Linearization and approximately 15 dBc/Hz phase noise suppression is demonstrated over a moderate phase noise LC VCO with a center frequency of 10 GHz.}}, author = {{Ayranci, Emre and Christensen, Kenn and Andreani, Pietro}}, booktitle = {{EUROCON, 2007. The International Conference on "Computer as a Tool"}}, isbn = {{978-1-4244-0813-9}}, language = {{eng}}, pages = {{2593--2599}}, title = {{Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop}}, url = {{http://dx.doi.org/10.1109/EURCON.2007.4400681}}, doi = {{10.1109/EURCON.2007.4400681}}, year = {{2007}}, }