Realization of a floating-point A/D converter
(2001) IEEE International Symposium on Circuits and Systems, ISCAS, 2001 1. p.404-407- Abstract
- A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1761984
- author
- Piper, Johan LU and Yuan, Jiren LU
- organization
- publishing date
- 2001
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings of 2001 IEEE International Symposium on Circuits and Systems
- volume
- 1
- pages
- 404 - 407
- conference name
- IEEE International Symposium on Circuits and Systems, ISCAS, 2001
- conference location
- Sydney, NSW, Australia
- conference dates
- 2001-05-06 - 2001-05-09
- external identifiers
-
- scopus:0035019266
- ISBN
- 0-7803-6685-9
- DOI
- 10.1109/ISCAS.2001.921878
- language
- English
- LU publication?
- yes
- id
- dd1eead0-83e9-4048-935a-1b179dee4695 (old id 1761984)
- date added to LUP
- 2016-04-04 13:54:21
- date last changed
- 2022-02-28 23:04:29
@inproceedings{dd1eead0-83e9-4048-935a-1b179dee4695, abstract = {{A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.}}, author = {{Piper, Johan and Yuan, Jiren}}, booktitle = {{Proceedings of 2001 IEEE International Symposium on Circuits and Systems}}, isbn = {{0-7803-6685-9}}, language = {{eng}}, pages = {{404--407}}, title = {{Realization of a floating-point A/D converter}}, url = {{http://dx.doi.org/10.1109/ISCAS.2001.921878}}, doi = {{10.1109/ISCAS.2001.921878}}, volume = {{1}}, year = {{2001}}, }