Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology

Meinerzhagen, Pascal ; Sherazi, Syed Muhammad Yasser LU ; Burg, Andreas and Rodrigues, Joachim LU (2011) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1(2). p.173-182
Abstract
In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed,

routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable... (More)
In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed,

routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs. (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
reliability, process parameter variations, sub-VT operation, Embedded memory, flip-flop array, latch array, low-power
in
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
volume
1
issue
2
pages
173 - 182
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:80052048123
ISSN
2156-3365
DOI
10.1109/JETCAS.2011.2162159
language
English
LU publication?
yes
id
7cc276fe-f487-44a4-a8d1-5aa7f6fc0c4b (old id 2026612)
date added to LUP
2016-04-01 09:54:05
date last changed
2022-02-09 20:42:42
@article{7cc276fe-f487-44a4-a8d1-5aa7f6fc0c4b,
  abstract     = {{In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed,<br/><br>
routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.}},
  author       = {{Meinerzhagen, Pascal and Sherazi, Syed Muhammad Yasser and Burg, Andreas and Rodrigues, Joachim}},
  issn         = {{2156-3365}},
  keywords     = {{reliability; process parameter variations; sub-VT operation; Embedded memory; flip-flop array; latch array; low-power}},
  language     = {{eng}},
  number       = {{2}},
  pages        = {{173--182}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Journal on Emerging and Selected Topics in Circuits and Systems}},
  title        = {{Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology}},
  url          = {{http://dx.doi.org/10.1109/JETCAS.2011.2162159}},
  doi          = {{10.1109/JETCAS.2011.2162159}},
  volume       = {{1}},
  year         = {{2011}},
}