Floating-Point Analog-to-Digital Converter
(2004)- Abstract
- To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution.
The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive... (More) - To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution.
The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive divider and amplifying the divider outputs by identical amplifiers. The outputs from the amplifiers are sampled individually. The selected sampled signal is then converted by a pipelined ADC. The result from the selection gives the exponent and the ADC output the mantissa of the floating-point number.
Issues on the specific problems of designing the proposed FP-ADC have been addressed, including a general discussion about a pipelined ADC along with its sub-blocks.
A thorough investigation of the distortion in a pipelined ADC due to static mismatches and systematic errors is also presented. The result of the investigation is a general approach on how to calculate the distortion in a pipelined ADC. The distortion analyses can be performed by both analytical methods and computer simulations.
A chip has been manufactured in a standard analog 0.35 µm CMOS process giving 10 bits of resolution, and a dynamic range corresponding to a 15-bit ADC. The sampling rate is 54 Ms/s using 330 mW of power. (Less) - Abstract (Swedish)
- Popular Abstract in Swedish
I denna avhandling har jag undersökt hur man kan utöka det dynamiska omfånget utan att öka noggrannheten i en analog-till-digital omvandlare med en flyttalsliknande lösning.
Den valda lösningen går ut på att man förstärker en analog insignal med flera oberoende analoga förstärkare med skilda förstärkningar. Sedan väljs den förstärkare som ger den starkaste utsignalen som inte är förvanskad. Den valda förstarkarens utsignal omvandlas sedan till en motsvarande digital signal. Den valda förstärkningen ger då exponenten och den digitala signalen mantissan i en digital flyttalsrepresentation av den analoga insignalen.
På detta sätt kan man mäta väldigt svaga och... (More) - Popular Abstract in Swedish
I denna avhandling har jag undersökt hur man kan utöka det dynamiska omfånget utan att öka noggrannheten i en analog-till-digital omvandlare med en flyttalsliknande lösning.
Den valda lösningen går ut på att man förstärker en analog insignal med flera oberoende analoga förstärkare med skilda förstärkningar. Sedan väljs den förstärkare som ger den starkaste utsignalen som inte är förvanskad. Den valda förstarkarens utsignal omvandlas sedan till en motsvarande digital signal. Den valda förstärkningen ger då exponenten och den digitala signalen mantissan i en digital flyttalsrepresentation av den analoga insignalen.
På detta sätt kan man mäta väldigt svaga och väldigt starka signaler med samma relativa noggrannhet.
Resultat från både teoretiska beräkningar och praktiska experiment i modern mikrochip-teknologi presenteras i avhandlingen. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/21878
- author
- Piper, Johan LU
- supervisor
- opponent
-
- Professor Signell, Svante, LECS, ESD, KTH, Stockholm
- organization
- publishing date
- 2004
- type
- Thesis
- publication status
- published
- subject
- keywords
- Electronics and Electrical technology, matching, binary weighting, dynamic range, resolution, distortion, pipeline, A/D-converter, floating-point, Elektronik och elektroteknik
- pages
- 181 pages
- publisher
- Department of Electroscience, Lund University
- defense location
- Room E:1406, E-building (Ole Römers väg 3), Lund Institute of Technology, Lund
- defense date
- 2004-11-19 10:15:00
- language
- English
- LU publication?
- yes
- id
- 9c96a67d-fee7-485f-a742-8662fd4ca88a (old id 21878)
- date added to LUP
- 2016-04-01 16:35:19
- date last changed
- 2018-11-21 20:42:35
@phdthesis{9c96a67d-fee7-485f-a742-8662fd4ca88a,
abstract = {{To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution.<br/><br>
<br/><br>
The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive divider and amplifying the divider outputs by identical amplifiers. The outputs from the amplifiers are sampled individually. The selected sampled signal is then converted by a pipelined ADC. The result from the selection gives the exponent and the ADC output the mantissa of the floating-point number.<br/><br>
<br/><br>
Issues on the specific problems of designing the proposed FP-ADC have been addressed, including a general discussion about a pipelined ADC along with its sub-blocks.<br/><br>
<br/><br>
A thorough investigation of the distortion in a pipelined ADC due to static mismatches and systematic errors is also presented. The result of the investigation is a general approach on how to calculate the distortion in a pipelined ADC. The distortion analyses can be performed by both analytical methods and computer simulations.<br/><br>
<br/><br>
A chip has been manufactured in a standard analog 0.35 µm CMOS process giving 10 bits of resolution, and a dynamic range corresponding to a 15-bit ADC. The sampling rate is 54 Ms/s using 330 mW of power.}},
author = {{Piper, Johan}},
keywords = {{Electronics and Electrical technology; matching; binary weighting; dynamic range; resolution; distortion; pipeline; A/D-converter; floating-point; Elektronik och elektroteknik}},
language = {{eng}},
publisher = {{Department of Electroscience, Lund University}},
school = {{Lund University}},
title = {{Floating-Point Analog-to-Digital Converter}},
url = {{https://lup.lub.lu.se/search/files/4716761/1472266.pdf}},
year = {{2004}},
}