A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
(2013) Norchip conference, 2012- Abstract
- Two branches of gated ring oscillators (GRO)
act as the delay lines in 2-dimension Vernier
time-to-digital converter (TDC). The proposed
architecture reduces dramatically the inherent latency of
vernier structure. The already small quantization noise of
the standard Vernier TDC is further first-order shaped by
the GRO operation. The TDC has been simulated in 90nm
CMOS technology. Operating from 50MHz reference
frequency, it achieves a resolution better than 2ps
assuming a signal bandwidth of 1.56MHz (OSR=16), for a
minimum current consumption of 1.8mA from 1.2V.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3130166
- author
- Lu, Ping LU ; Liscidini, Antonio and Andreani, Pietro LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Digitall PLL, TDC, GRO, 2-dimention
- host publication
- NORCHIP 2012
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Norchip conference, 2012
- conference location
- Copenhagen, Denmark
- conference dates
- 2012-11-12 - 2012-11-13
- external identifiers
-
- scopus:84873533579
- ISBN
- 978-1-4673-2223-2
- 978-1-4673-2221-8
- DOI
- 10.1109/NORCHP.2012.6403120
- language
- English
- LU publication?
- yes
- id
- 1c33fdf2-a482-49f5-8e14-262b77c63ac1 (old id 3130166)
- date added to LUP
- 2016-04-04 12:52:07
- date last changed
- 2024-01-05 07:56:36
@inproceedings{1c33fdf2-a482-49f5-8e14-262b77c63ac1, abstract = {{Two branches of gated ring oscillators (GRO)<br/><br> act as the delay lines in 2-dimension Vernier<br/><br> time-to-digital converter (TDC). The proposed<br/><br> architecture reduces dramatically the inherent latency of<br/><br> vernier structure. The already small quantization noise of<br/><br> the standard Vernier TDC is further first-order shaped by<br/><br> the GRO operation. The TDC has been simulated in 90nm<br/><br> CMOS technology. Operating from 50MHz reference<br/><br> frequency, it achieves a resolution better than 2ps<br/><br> assuming a signal bandwidth of 1.56MHz (OSR=16), for a<br/><br> minimum current consumption of 1.8mA from 1.2V.}}, author = {{Lu, Ping and Liscidini, Antonio and Andreani, Pietro}}, booktitle = {{NORCHIP 2012}}, isbn = {{978-1-4673-2223-2}}, keywords = {{Digitall PLL; TDC; GRO; 2-dimention}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter}}, url = {{http://dx.doi.org/10.1109/NORCHP.2012.6403120}}, doi = {{10.1109/NORCHP.2012.6403120}}, year = {{2013}}, }