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Efficient scalable approximate multipliers via significance-driven partial product removal

Castillo Mohedano, Sergio LU ; Åberg, Victor LU orcid ; Rodrigues, Joachim LU and Nouripayam, Masoud LU (2026)
Abstract
Multipliers are key components in compute-intensive applications but incur high hardware cost. In error-tolerant domains such as image processing, approximate computing enables significant efficiency gains. This work presents a scalable approximate multiplier based on a deterministic, priority-driven partial product removal algorithm. The method assesses an extensive design-space exploration and automatically identifies and removes less significant partial product rows across different operand widths while keeping errors bounded. Gate-level evaluation of an 8×8 design in 22 nm technology shows 87% reduction in power-area-delay product (PADP) compared to an exact Dadda multiplier, with a mean relative error distance (MRED) of 2.27%. The... (More)
Multipliers are key components in compute-intensive applications but incur high hardware cost. In error-tolerant domains such as image processing, approximate computing enables significant efficiency gains. This work presents a scalable approximate multiplier based on a deterministic, priority-driven partial product removal algorithm. The method assesses an extensive design-space exploration and automatically identifies and removes less significant partial product rows across different operand widths while keeping errors bounded. Gate-level evaluation of an 8×8 design in 22 nm technology shows 87% reduction in power-area-delay product (PADP) compared to an exact Dadda multiplier, with a mean relative error distance (MRED) of 2.27%. The proposed design achieves a superior accuracy-efficiency trade-off compared to state-of-the-art approximate multipliers. Validation using image processing tasks (smoothing and motion filtering) demonstrates high output fidelity with negligible visual degradation. (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
in press
subject
host publication
2026 IFIP/IEEE International Conference on Very Large Scale Integration SoC (VLSI-SoC)
pages
6 pages
language
English
LU publication?
yes
id
480990cf-a999-46d2-ac8e-79d005bacdf4
date added to LUP
2026-08-26 10:50:28
date last changed
2026-09-10 08:22:04
@inproceedings{480990cf-a999-46d2-ac8e-79d005bacdf4,
  abstract     = {{Multipliers are key components in compute-intensive applications but incur high hardware cost. In error-tolerant domains such as image processing, approximate computing enables significant efficiency gains. This work presents a scalable approximate multiplier based on a deterministic, priority-driven partial product removal algorithm. The method assesses an extensive design-space exploration and automatically identifies and removes less significant partial product rows across different operand widths while keeping errors bounded. Gate-level evaluation of an 8×8 design in 22 nm technology shows 87% reduction in power-area-delay product (PADP) compared to an exact Dadda multiplier, with a mean relative error distance (MRED) of 2.27%. The proposed design achieves a superior accuracy-efficiency trade-off compared to state-of-the-art approximate multipliers. Validation using image processing tasks (smoothing and motion filtering) demonstrates high output fidelity with negligible visual degradation.}},
  author       = {{Castillo Mohedano, Sergio and Åberg, Victor and Rodrigues, Joachim and Nouripayam, Masoud}},
  booktitle    = {{2026 IFIP/IEEE International Conference on Very Large Scale Integration SoC (VLSI-SoC)}},
  language     = {{eng}},
  title        = {{Efficient scalable approximate multipliers via significance-driven partial product removal}},
  year         = {{2026}},
}