Design considerations of a floating-point ADC with embedded S/H
(2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 p.6166-6169- Abstract
- This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/615671
- author
- Piper, Johan LU and Yuan, Jiren LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- resistive weighting, chopped gain stages, input referred thermal noise, channel matching, ADC distortion, settling time, delay, floating-point ADC, embedded S/H, offset matching, robust channel selecting logic
- host publication
- IEEE International Symposium on Circuits and Systems (ISCAS)
- pages
- 6166 - 6169
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2005
- conference location
- Kobe, Japan
- conference dates
- 2005-05-23 - 2005-05-26
- external identifiers
-
- wos:000232002405204
- scopus:57849127823
- ISBN
- 0-7803-8834-8
- DOI
- 10.1109/ISCAS.2005.1466048
- language
- English
- LU publication?
- yes
- id
- 8829065d-46de-4a31-95c2-fa6c97877007 (old id 615671)
- date added to LUP
- 2016-04-04 11:45:30
- date last changed
- 2022-04-24 01:07:33
@inproceedings{8829065d-46de-4a31-95c2-fa6c97877007, abstract = {{This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested}}, author = {{Piper, Johan and Yuan, Jiren}}, booktitle = {{IEEE International Symposium on Circuits and Systems (ISCAS)}}, isbn = {{0-7803-8834-8}}, keywords = {{resistive weighting; chopped gain stages; input referred thermal noise; channel matching; ADC distortion; settling time; delay; floating-point ADC; embedded S/H; offset matching; robust channel selecting logic}}, language = {{eng}}, pages = {{6166--6169}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Design considerations of a floating-point ADC with embedded S/H}}, url = {{http://dx.doi.org/10.1109/ISCAS.2005.1466048}}, doi = {{10.1109/ISCAS.2005.1466048}}, year = {{2005}}, }