InAs WRAP-gate nanowire transistors
(2007) IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials p.527-529- Abstract
- InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN<sub>x</sub> layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V<sub>sd</sub>=0.5V. The transistors operate in depletion mode. © 2007 IEEE.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/643428
- author
- Wernersson, Lars-Erik LU
- organization
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Drive currents, Nanowire transistors, WRAP-gate nanowire, Scalable technologies
- host publication
- Conference Proceedings - International Conference on Indium Phosphide and Related Materials
- pages
- 527 - 529
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IPRM'07: IEEE 19th International Conference on Indium Phosphide and Related Materials
- conference location
- Matsue, Japan
- conference dates
- 2007-05-14 - 2007-05-18
- external identifiers
-
- wos:000248523100139
- other:CODEN: CPRMEG
- scopus:34748887765
- ISSN
- 1092-8669
- DOI
- 10.1109/ICIPRM.2007.381244
- language
- English
- LU publication?
- yes
- id
- de41eabd-8461-48a5-8cd9-4406660bd6fe (old id 643428)
- date added to LUP
- 2016-04-01 16:22:59
- date last changed
- 2022-01-28 19:17:48
@inproceedings{de41eabd-8461-48a5-8cd9-4406660bd6fe, abstract = {{InAs nanowire wrap-gate transistors have been fabricated in a vertical geometry using matrices of 11×11 nanowires. The fabrication process is based on conventional and scalable technologies that are adopted for the nanowire transistors. A SiN<sub>x</sub> layer is used as gate dielectric and a wrap-gate of 80 nm gate length is formed. These transistors show good DC characteristics with drive currents above 1 mA and a transconductance of 0.28 mS at V<sub>sd</sub>=0.5V. The transistors operate in depletion mode. © 2007 IEEE.}}, author = {{Wernersson, Lars-Erik}}, booktitle = {{Conference Proceedings - International Conference on Indium Phosphide and Related Materials}}, issn = {{1092-8669}}, keywords = {{Drive currents; Nanowire transistors; WRAP-gate nanowire; Scalable technologies}}, language = {{eng}}, pages = {{527--529}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{InAs WRAP-gate nanowire transistors}}, url = {{http://dx.doi.org/10.1109/ICIPRM.2007.381244}}, doi = {{10.1109/ICIPRM.2007.381244}}, year = {{2007}}, }