A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands
(2019) In IEEE Transactions on Circuits and Systems I: Regular Papers 66(7). p.2763-2774- Abstract
- A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of... (More)
- A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28 nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/e7d3c481-f269-416b-aab0-c36414695a4a
- author
- Mahdavi, Mojtaba LU ; Edfors, Ove LU ; Öwall, Viktor LU and Liu, Liang LU
- organization
- publishing date
- 2019-02-27
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- FFT processor, massive MIMO, low latency, pipelined architecture, ASIC implementation, OFDM, guard band, VLSI architecture, hardware implementation
- in
- IEEE Transactions on Circuits and Systems I: Regular Papers
- volume
- 66
- issue
- 7
- pages
- 12 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85067983787
- ISSN
- 1558-0806
- DOI
- 10.1109/TCSI.2019.2896042
- language
- English
- LU publication?
- yes
- id
- e7d3c481-f269-416b-aab0-c36414695a4a
- date added to LUP
- 2019-03-21 02:00:58
- date last changed
- 2024-04-01 23:55:31
@article{e7d3c481-f269-416b-aab0-c36414695a4a, abstract = {{A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28 nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures.}}, author = {{Mahdavi, Mojtaba and Edfors, Ove and Öwall, Viktor and Liu, Liang}}, issn = {{1558-0806}}, keywords = {{FFT processor; massive MIMO; low latency; pipelined architecture; ASIC implementation; OFDM; guard band; VLSI architecture; hardware implementation}}, language = {{eng}}, month = {{02}}, number = {{7}}, pages = {{2763--2774}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Transactions on Circuits and Systems I: Regular Papers}}, title = {{A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands}}, url = {{http://dx.doi.org/10.1109/TCSI.2019.2896042}}, doi = {{10.1109/TCSI.2019.2896042}}, volume = {{66}}, year = {{2019}}, }