Jörn Janneck (Former)

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2013
Mark MPEG Reconfigurable Video Coding
Mattavelli, Marco ; Raulet, Mickaël and Janneck, Jörn ^LU (2013) p.281-314
- Chapter in Book/Report/Conference proceeding › Book chapter
Mark Buffer Optimization Based on Critical Path Analysis of a Dataflow Program Design
Brunet, Simone Casale ; Mattavelli, Marco and Janneck, Jörn ^LU (2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Automatic queue sizing for dataflow applications
Miller, Ian D. ; Janneck, Jörn ^LU and Parlour, David B. (2013) US 8,595,391
- Patent › Patent
Mark High-level Synthesis of Dataflow Programs for Signal Processing Systems
Bezati, Endri ; Mattavelli, Marco and Janneck, Jörn ^LU (2013) 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013)
- Contribution to conference › Paper, not in proceeding
Mark Design Space Exploration of High-Level Stream Programs on Parallel Architectures
Brunet, Simone Casale ; Alberti, Claudio ; Mattavelli, Marco and Janneck, Jörn ^LU (2013) 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013)
- Contribution to conference › Paper, not in proceeding
Mark Method and apparatus for processing an event notification in a concurrent processing system
Parlour, David B. ; Janneck, Jörn ^LU and Miller, Ian D. (2013) US 8,572,432
- Patent › Patent
Mark TURNUS: a Design Exploration Framework for Dataflow System Design
Brunet, Simone Casale ; Mattavelli, Marco and Janneck, Jörn ^LU (2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Systems Design Space Exploration by Serial Dataflow Program Executions
Brunet, Simone Casale ; Mattavelli, Marco ; Alberti, Claudio and Janneck, Jörn ^LU (2013) 47th Annual Asilomar Conference on Signals, Systems, and Computers, 2003
- Contribution to conference › Paper, not in proceeding
Mark Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit
Janneck, Jörn ^LU ; Parlour, David B and Schumacher, Paul R (2013) U.S. Patent 8,402,409
- Patent › Patent
Mark Multi-Clock-Domain Optimization for Reconfigurable Architectures in High-Level Dataflow Applications
Brunet, Simone Casale ; Bezati, Endri ; Alberti, Claudio ; Mattavelli, Marco ; Amaldi, Eduardo and Janneck, Jörn ^LU (2013) 47th Annual Asilomar Conference on Signals, Systems, and Computers, 2003
- Contribution to conference › Paper, not in proceeding