Pietro Andreani
51 – 60 of 163
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2012
-
Mark
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
(
- Contribution to journal › Article
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
-
Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
(
- Contribution to journal › Article
-
Mark
A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
(
- Contribution to journal › Article
-
Mark
A mixed mode design flow for multi GHz ADPLLs
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding