Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Ghani Zadegan, Farrokh LU ; Zhang, Zilin ; Peterse ́n, Kim and Larsson, Erik LU
(2022)
p.219-228
- Abstract
- Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing... (More)
- Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/036b6286-fc41-4717-8b67-5fe01f24237a
- author
- Ghani Zadegan, Farrokh
LU
; Zhang, Zilin
; Peterse ́n, Kim
and Larsson, Erik
LU
- organization
- publishing date
- 2022
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings - International Test Conference
- pages
- 10 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85146148252
- ISBN
- 978-166546270-9
- DOI
- 10.1109/ITC50671.2022.00030
- language
- English
- LU publication?
- yes
- id
- 036b6286-fc41-4717-8b67-5fe01f24237a
- date added to LUP
- 2022-07-29 10:21:07
- date last changed
- 2023-02-16 09:49:25
@inproceedings{036b6286-fc41-4717-8b67-5fe01f24237a,
abstract = {{Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters.}},
author = {{Ghani Zadegan, Farrokh and Zhang, Zilin and Peterse ́n, Kim and Larsson, Erik}},
booktitle = {{Proceedings - International Test Conference}},
isbn = {{978-166546270-9}},
language = {{eng}},
pages = {{219--228}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus}},
url = {{https://lup.lub.lu.se/search/files/124732231/2022145858.pdf}},
doi = {{10.1109/ITC50671.2022.00030}},
year = {{2022}},
}