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InGaAs Nanowire and Quantum Well Devices

Södergren, Lasse LU (2022)
Abstract
To fulfill the increasing demand for high-speed electronics used for computation or communication is one everlasting challenge for the semiconductor industry. Emerging fields such as quantum computation also has a need for circuits operating at cryogenic temperatures. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the main component in modern electronics, traditionally fabricated in Si. However, III-V materials generally exhibits higher electron mobility compared to Si. This enables the realization of MOSFETs with higher operational speed or lower power consumption. While a nanowire geometry, where the channel is gated from multiple sides brings an increase in the electrostatic gate control, allowing for further gate... (More)
To fulfill the increasing demand for high-speed electronics used for computation or communication is one everlasting challenge for the semiconductor industry. Emerging fields such as quantum computation also has a need for circuits operating at cryogenic temperatures. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the main component in modern electronics, traditionally fabricated in Si. However, III-V materials generally exhibits higher electron mobility compared to Si. This enables the realization of MOSFETs with higher operational speed or lower power consumption. While a nanowire geometry, where the channel is gated from multiple sides brings an increase in the electrostatic gate control, allowing for further gate length scaling. In this thesis, lateral InGaAs nanowire and quantum well devices have been fabricated and characterized with the purpose of understanding the electron transport and its limitations over a wide temperature range. MOSFETs at cryogenic temperatures, where the phonon occupation is low, are highly sensitive to disorder and defects in the semiconductor/oxide interface. InGaAs RF MOSFETs with different spacer technologies for reducing capacitances have also been fabricated and characterized. Optimizing the spacers for low capacitance and low access resistance is a key design consideration when fabricating devices for high-frequency operation. (Less)
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author
supervisor
opponent
  • Associate Prof. Kim, Sanghyeon, KAIST, South Korea.
organization
publishing date
type
Thesis
publication status
published
subject
keywords
nanowire, quantum well, cryogenic, III-V, InGaAs, MOSFET, MOVPE, Hall, mobility, ballistic, RF
publisher
Lund University
defense location
Lecture Hall E:1406, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund.
defense date
2022-06-17 09:00:00
ISBN
978-91-8039-297-6
978-91-8039-296-9
language
English
LU publication?
yes
id
044333ed-5efa-4312-a325-435c31d43b6d
date added to LUP
2022-05-16 11:16:21
date last changed
2023-02-23 15:21:48
@phdthesis{044333ed-5efa-4312-a325-435c31d43b6d,
  abstract     = {{To fulfill the increasing demand for high-speed electronics used for computation or communication is one everlasting challenge for the semiconductor industry. Emerging fields such as quantum computation also has a need for circuits operating at cryogenic temperatures. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the main component in modern electronics, traditionally fabricated in Si. However, III-V materials generally exhibits higher electron mobility compared to Si. This enables the realization of MOSFETs with higher operational speed or lower power consumption. While a nanowire geometry, where the channel is gated from multiple sides brings an increase in the electrostatic gate control, allowing for further gate length scaling. In this thesis, lateral InGaAs nanowire and quantum well devices have been fabricated and characterized with the purpose of understanding the electron transport and its limitations over a wide temperature range. MOSFETs at cryogenic temperatures, where the phonon occupation is low, are highly sensitive to disorder and defects in the semiconductor/oxide interface. InGaAs RF MOSFETs with different spacer technologies for reducing capacitances have also been fabricated and characterized. Optimizing the spacers for low capacitance and low access resistance is a key design consideration when fabricating devices for high-frequency operation.}},
  author       = {{Södergren, Lasse}},
  isbn         = {{978-91-8039-297-6}},
  keywords     = {{nanowire; quantum well; cryogenic; III-V; InGaAs; MOSFET; MOVPE; Hall; mobility; ballistic; RF}},
  language     = {{eng}},
  publisher    = {{Lund University}},
  school       = {{Lund University}},
  title        = {{InGaAs Nanowire and Quantum Well Devices}},
  url          = {{https://lup.lub.lu.se/search/files/118680867/Thesis_Lasse_Sodergren_Final_censored_pdf.pdf}},
  year         = {{2022}},
}