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A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier

Andreani, Pietro LU and Sundström, Lars (2000) In Analog Integrated Circuits and Signal Processing 22(1). p.25-30
Abstract
This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 mu m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V... (More)
This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 mu m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Analog Integrated Circuits and Signal Processing
volume
22
issue
1
pages
25 - 30
publisher
Springer
external identifiers
  • scopus:0033640517
ISSN
0925-1030
DOI
10.1023/A:1008315925581
language
English
LU publication?
yes
id
2609572b-de13-44e4-9e72-bafa8c2472f3 (old id 1051602)
date added to LUP
2008-04-03 13:21:19
date last changed
2017-01-01 07:45:11
@article{2609572b-de13-44e4-9e72-bafa8c2472f3,
  abstract     = {This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 mu m CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.},
  author       = {Andreani, Pietro and Sundström, Lars},
  issn         = {0925-1030},
  language     = {eng},
  number       = {1},
  pages        = {25--30},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier},
  url          = {http://dx.doi.org/10.1023/A:1008315925581},
  volume       = {22},
  year         = {2000},
}