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Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain

Sherazi, Syed Muhammad Yasser LU ; Rodrigues, Joachim LU ; Akgun, OmerCan LU ; Sjöland, Henrik LU and Nilsson, Peter LU (2013) In Microprocessors and Microsystems 37(4-5). p.494-504
Abstract
This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy

model is applied to characterize the designs in the sub-VT domain. Simulation results show that

the unfolded by 2 and 4 architectures are the most energy efficient for throughput requirements between 250 ksamples/s, and 2Msamples/s. By the selection of optimum... (More)
This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy

model is applied to characterize the designs in the sub-VT domain. Simulation results show that

the unfolded by 2 and 4 architectures are the most energy efficient for throughput requirements between 250 ksamples/s, and 2Msamples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164 fJ and 205 fJ, with single supply voltage of 260mV. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Energy dissipation, Ultra Low Power, Decimation filters, Half band filters, 65 nm, Sub-threshold, CMOS, Unfolding, Wireless devices, Implantable devices.
in
Microprocessors and Microsystems
volume
37
issue
4-5
pages
494 - 504
publisher
Elsevier
external identifiers
  • wos:000324667900011
  • scopus:84878593576
ISSN
0141-9331
DOI
10.1016/j.micpro.2012.04.002
project
EIT_UPD Wireless Communication for Ultra Portable Devices
language
English
LU publication?
yes
id
11b745b8-4f3e-4ada-80b4-457e8a03a0f9 (old id 2437930)
date added to LUP
2012-04-05 13:48:05
date last changed
2019-04-30 21:25:49
@article{11b745b8-4f3e-4ada-80b4-457e8a03a0f9,
  abstract     = {This paper presents an analysis of energy dissipation of a decimation filter chain of four half band digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy<br/><br>
model is applied to characterize the designs in the sub-VT domain. Simulation results show that<br/><br>
the unfolded by 2 and 4 architectures are the most energy efficient for throughput requirements between 250 ksamples/s, and 2Msamples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164 fJ and 205 fJ, with single supply voltage of 260mV.},
  author       = {Sherazi, Syed Muhammad Yasser and Rodrigues, Joachim and Akgun, OmerCan and Sjöland, Henrik and Nilsson, Peter},
  issn         = {0141-9331},
  keyword      = {Energy dissipation,Ultra Low Power,Decimation filters,Half band filters,65 nm,Sub-threshold,CMOS,Unfolding,Wireless devices,Implantable devices.},
  language     = {eng},
  number       = {4-5},
  pages        = {494--504},
  publisher    = {Elsevier},
  series       = {Microprocessors and Microsystems},
  title        = {Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain},
  url          = {http://dx.doi.org/10.1016/j.micpro.2012.04.002},
  volume       = {37},
  year         = {2013},
}