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Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters

Sherazi, Syed Muhammad Yasser LU ; Rodrigues, Joachim LU ; Akgun, OmerCan LU ; Sjöland, Henrik LU and Nilsson, Peter LU (2010) NORCHIP Conference, 2010 In [Host publication title missing]
Abstract
This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-

VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4... (More)
This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-

VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy

than any other implementation in this speed range. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
High Threshold standard cells, Digital Filters, CMOS, Sub-Threshold, 65 nm, Design Exploration, Ultra Low Energy, Throughput
in
[Host publication title missing]
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
NORCHIP Conference, 2010
external identifiers
  • Scopus:78751532694
ISBN
978-1-4244-8972-5
DOI
10.1109/NORCHIP.2010.5669452
language
English
LU publication?
yes
id
45c28cf9-36c9-4bf7-9616-2f02450e64ff (old id 1689549)
date added to LUP
2010-10-05 10:11:08
date last changed
2017-01-01 07:56:54
@inproceedings{45c28cf9-36c9-4bf7-9616-2f02450e64ff,
  abstract     = {This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-<br/><br>
VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy<br/><br>
than any other implementation in this speed range.},
  author       = {Sherazi, Syed Muhammad Yasser and Rodrigues, Joachim and Akgun, OmerCan and Sjöland, Henrik and Nilsson, Peter},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4244-8972-5},
  keyword      = {High Threshold standard cells,Digital Filters,CMOS,Sub-Threshold,65 nm,Design Exploration,Ultra Low Energy,Throughput},
  language     = {eng},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters},
  url          = {http://dx.doi.org/10.1109/NORCHIP.2010.5669452},
  year         = {2010},
}