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Scheduling Tests for 3D Stacked Chips under Power Constraints

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2011) 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011) In [Host publication title missing] p.72-77
Abstract
This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines... (More)
This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Design for Test (DfT), Built in Self Test (BIST), Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV).
in
[Host publication title missing]
pages
72 - 77
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
6th International Symposium on Electronic Design, Test and Applications (DELTA 2011)
external identifiers
  • Scopus:79953142127
ISBN
978-1-4244-9357-9
DOI
10.1109/DELTA.2011.23
language
English
LU publication?
no
id
a910d2e8-0ba8-45bd-9907-3da2c3e48af9 (old id 2340779)
date added to LUP
2012-02-10 13:45:23
date last changed
2017-02-19 04:31:30
@inproceedings{a910d2e8-0ba8-45bd-9907-3da2c3e48af9,
  abstract     = {This paper addresses Test Application Time (TAT)reduction for core-based 3D Stacked ICs (SICs). Applyingtraditional test scheduling methods used for non-stacked chiptesting where the same test schedule is applied both at wafer testand at final test to SICs, leads to unnecessarily high TAT. This isbecause the final test of 3D-SICs includes the testing of all thestacked chips. A key challenge in 3D-SIC testing is to reduce TATby co-optimizing the wafer test and the final test while meetingpower constraints. We consider a system of chips with coresequipped with dedicated Built-In-Self-Test (BIST)-engines andpropose a test scheduling approach to reduce TAT while meetingthe power constraints. Depending on the test schedule, the controllines that are required for BIST can be shared among severalBIST engines. This is taken into account in the test schedulingapproach and experiments show significant savings in TAT.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4244-9357-9},
  keyword      = {Design for Test (DfT),Built in Self Test (BIST),Test scheduling,Sessions,Test time,Test cost,3D Stacked Integrated Circuit (SIC),Through Silicon Via (TSV).},
  language     = {eng},
  pages        = {72--77},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Scheduling Tests for 3D Stacked Chips under Power Constraints},
  url          = {http://dx.doi.org/10.1109/DELTA.2011.23},
  year         = {2011},
}