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Defect Probability-based System-On-Chip Test Scheduling

Larsson, Erik LU ; Pouget, Julien and Peng, Zebo (2003) 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003 p.25-32
Abstract
In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed... (More)
In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to conference
publication status
published
subject
keywords
system-on-chip, testing, defect-detection, sequential scheduling, concurrent scheduling
pages
25 - 32
conference name
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003
language
English
LU publication?
no
id
45c5abda-50dd-4df7-9603-532f72c29704 (old id 2341122)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/ddecs03.pdf
date added to LUP
2012-02-10 13:29:53
date last changed
2016-06-29 08:56:38
@misc{45c5abda-50dd-4df7-9603-532f72c29704,
  abstract     = {In this paper we address the test scheduling problem for system-on-chip. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test set in order to schedule the test sets so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. Concurrent scheduling), and test set assumptions (fixed test time vs. Flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.},
  author       = {Larsson, Erik and Pouget, Julien and Peng, Zebo},
  keyword      = {system-on-chip,testing,defect-detection,sequential scheduling,concurrent scheduling},
  language     = {eng},
  pages        = {25--32},
  title        = {Defect Probability-based System-On-Chip Test Scheduling},
  year         = {2003},
}