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Test Resource Partitioning and Optimization for SOC Designs

Larsson, Erik LU and Fujiwara, Hideo (2003) 2003 IEEE VLSI Test Symposium VTS03 p.319-319
Abstract
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
core-based design, resource floor-planning, test access mechanism, TAM, test scheduling, TAM routing
host publication
[Host publication title missing]
pages
319 - 319
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2003 IEEE VLSI Test Symposium VTS03
conference location
Napa, CA, United States
conference dates
2003-04-27 - 2003-05-01
external identifiers
  • scopus:84943549327
ISSN
1093-0167
ISBN
0-7695-1924-5
DOI
10.1109/VTEST.2003.1197669
language
English
LU publication?
no
id
128cdf29-eada-40d4-8538-5218f4f65bc7 (old id 2341126)
date added to LUP
2016-04-01 16:13:33
date last changed
2020-01-12 19:09:42
@inproceedings{128cdf29-eada-40d4-8538-5218f4f65bc7,
  abstract     = {We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.},
  author       = {Larsson, Erik and Fujiwara, Hideo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-1924-5},
  issn         = {1093-0167},
  language     = {eng},
  pages        = {319--319},
  publisher    = {IEEE - Institute of Electrical and Electronics Engineers Inc.},
  title        = {Test Resource Partitioning and Optimization for SOC Designs},
  url          = {http://dx.doi.org/10.1109/VTEST.2003.1197669},
  doi          = {10.1109/VTEST.2003.1197669},
  year         = {2003},
}