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2014
Mark Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) p.1-6
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2013
Mark Embedded DfT Instrumentation: Design, Access, Retargeting and Case Studies
Larsson, Erik ^LU and Keim, Martin (2013) VLSI Test Symposium (VTS)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2004
Mark Defect-Aware SOC Test Scheduling
Larsson, Erik ^LU ; Pouget, Julien and Peng, Zebo (2004) 2004 IEEE VLSI Test Symposium VTS04 p.359-364
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2003
Mark Test Resource Partitioning and Optimization for SOC Designs
Larsson, Erik ^LU and Fujiwara, Hideo (2003) 2003 IEEE VLSI Test Symposium VTS03 p.319-319
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding