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A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

Lu, Ping LU ; Wu, Ying and Andreani, Pietro LU (2012) IEEE International Symposium on Circuits and Systems (ISCAS), 2012 In [Host publication title missing] p.2593-2596
Abstract
This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally, an automatic tuning bank controller selects the active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The equivalent in-band phase noise at 2.7GHz is -110dBc/Hz with a reference clock of 25MHz. The digital PLL is simulated in a 90nm CMOS process, indicating a current consumption of 21mA from a... (More)
This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally, an automatic tuning bank controller selects the active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The equivalent in-band phase noise at 2.7GHz is -110dBc/Hz with a reference clock of 25MHz. The digital PLL is simulated in a 90nm CMOS process, indicating a current consumption of 21mA from a 1.2V supply. (Less)
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Chapter in Book/Report/Conference proceeding
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published
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in
[Host publication title missing]
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2012
external identifiers
  • wos:000316903702197
  • scopus:84866596168
ISSN
0271-4310
2158-1525
language
English
LU publication?
yes
id
2cdc87d3-ad92-4f2c-978c-b6bc80e79241 (old id 2437191)
alternative location
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6271835&contentType=Conference+Publications&queryText%3DA+90nm+CMOS+Digital+PLL+Based+on+Vernier-Gated-Ring-Oscillator+Time-to-Digital+Converter
date added to LUP
2012-04-04 14:40:02
date last changed
2017-01-15 03:11:29
@inproceedings{2cdc87d3-ad92-4f2c-978c-b6bc80e79241,
  abstract     = {This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally, an automatic tuning bank controller selects the active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The equivalent in-band phase noise at 2.7GHz is -110dBc/Hz with a reference clock of 25MHz. The digital PLL is simulated in a 90nm CMOS process, indicating a current consumption of 21mA from a 1.2V supply.},
  author       = {Lu, Ping and Wu, Ying and Andreani, Pietro},
  booktitle    = {[Host publication title missing]},
  issn         = {0271-4310},
  language     = {eng},
  pages        = {2593--2596},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter},
  year         = {2012},
}