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A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps

Lu, Ping LU ; Liscidini, Antonio and Andreani, Pietro LU (2012) In IEEE Journal of Solid-State Circuits 47(7). p.1626-1635
Abstract
Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Gated Ring Oscillator, Time-to-Digital Converter, Vernier Delay Line
in
IEEE Journal of Solid-State Circuits
volume
47
issue
7
pages
1626 - 1635
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000306913500012
ISSN
0018-9200
language
English
LU publication?
yes
id
9e259782-10c6-47a7-93b5-c7127f05fe13 (old id 2437658)
alternative location
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6193181&contentType=Journals+%26+Magazines&queryText%3DA+3.6mW%2C+90nm+CMOS+Gated-Vernier+Time-to-Digital+Converter
date added to LUP
2012-04-05 13:45:58
date last changed
2016-04-16 06:45:37
@article{9e259782-10c6-47a7-93b5-c7127f05fe13,
  abstract     = {Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.},
  author       = {Lu, Ping and Liscidini, Antonio and Andreani, Pietro},
  issn         = {0018-9200},
  keyword      = {Gated Ring Oscillator,Time-to-Digital Converter,Vernier Delay Line},
  language     = {eng},
  number       = {7},
  pages        = {1626--1635},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps},
  volume       = {47},
  year         = {2012},
}