A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(2012) In IEEE Journal of Solid-State Circuits 47(7). p.1626-1635- Abstract
- Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2437658
- author
- Lu, Ping LU ; Liscidini, Antonio and Andreani, Pietro LU
- organization
- publishing date
- 2012
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Gated Ring Oscillator, Time-to-Digital Converter, Vernier Delay Line
- in
- IEEE Journal of Solid-State Circuits
- volume
- 47
- issue
- 7
- pages
- 1626 - 1635
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000306913500012
- scopus:84862984855
- ISSN
- 0018-9200
- language
- English
- LU publication?
- yes
- id
- 9e259782-10c6-47a7-93b5-c7127f05fe13 (old id 2437658)
- alternative location
- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6193181&contentType=Journals+%26+Magazines&queryText%3DA+3.6mW%2C+90nm+CMOS+Gated-Vernier+Time-to-Digital+Converter
- date added to LUP
- 2016-04-04 09:28:24
- date last changed
- 2022-05-01 17:32:23
@article{9e259782-10c6-47a7-93b5-c7127f05fe13, abstract = {{Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS process and consumes 3mA from 1.2V when operating at 25MHz. The native Vernier resolution of the TDC is 5.8ps, while the total noise integrated over a bandwidth of 800kHz yields an equivalent TDC resolution of 3.2ps.}}, author = {{Lu, Ping and Liscidini, Antonio and Andreani, Pietro}}, issn = {{0018-9200}}, keywords = {{Gated Ring Oscillator; Time-to-Digital Converter; Vernier Delay Line}}, language = {{eng}}, number = {{7}}, pages = {{1626--1635}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Journal of Solid-State Circuits}}, title = {{A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps}}, url = {{http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6193181&contentType=Journals+%26+Magazines&queryText%3DA+3.6mW%2C+90nm+CMOS+Gated-Vernier+Time-to-Digital+Converter}}, volume = {{47}}, year = {{2012}}, }