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Scheduling Tests for 3D Stacked Chips under Power Constraints

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2012) In Journal of Electronic Testing 28(1). p.121-135
Abstract
This paper addresses Test Application Time (TAT) reduction under power constraints for core- based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the T AT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed... (More)
This paper addresses Test Application Time (TAT) reduction under power constraints for core- based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the T AT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastruc- ture and propose a test scheduling approach to reduce T AT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant sav- ings in T AT. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
3D integration, Power constrained test scheduling
in
Journal of Electronic Testing
volume
28
issue
1
pages
121 - 135
publisher
Springer
external identifiers
  • wos:000302868800011
  • scopus:84857786763
ISSN
0923-8174
DOI
10.1007/s10836-011-5244-5
language
English
LU publication?
yes
id
7aef11bd-fe52-4dc2-ae5c-e4a9ac6ae8ab (old id 2518140)
date added to LUP
2012-06-07 11:22:23
date last changed
2017-02-19 03:07:00
@article{7aef11bd-fe52-4dc2-ae5c-e4a9ac6ae8ab,
  abstract     = {This paper addresses Test Application Time (TAT) reduction under power constraints for core- based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the T AT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastruc- ture and propose a test scheduling approach to reduce T AT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant sav- ings in T AT.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  issn         = {0923-8174},
  keyword      = {3D integration,Power constrained test scheduling},
  language     = {eng},
  number       = {1},
  pages        = {121--135},
  publisher    = {Springer},
  series       = {Journal of Electronic Testing},
  title        = {Scheduling Tests for 3D Stacked Chips under Power Constraints},
  url          = {http://dx.doi.org/10.1007/s10836-011-5244-5},
  volume       = {28},
  year         = {2012},
}