Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
(2013) In Analog Integrated Circuits and Signal Processing 76(3). p.353-366- Abstract
- This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of... (More)
- This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3990573
- author
- Andersson, Mattias LU ; Sundström, Lars ; Andersson, Martin LU and Andreani, Pietro LU
- organization
- publishing date
- 2013
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Analog Integrated Circuits and Signal Processing
- volume
- 76
- issue
- 3
- pages
- 353 - 366
- publisher
- Springer
- external identifiers
-
- wos:000323652500009
- scopus:84883488826
- ISSN
- 0925-1030
- DOI
- 10.1007/s10470-013-0114-y
- project
- EIT_DRAGON Digital Radio Architectures Going Nanoscale
- language
- English
- LU publication?
- yes
- id
- 2c6859a3-f32c-4dc3-8539-04805b5a5ad4 (old id 3990573)
- date added to LUP
- 2016-04-01 13:51:26
- date last changed
- 2022-03-29 17:49:45
@article{2c6859a3-f32c-4dc3-8539-04805b5a5ad4, abstract = {{This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.}}, author = {{Andersson, Mattias and Sundström, Lars and Andersson, Martin and Andreani, Pietro}}, issn = {{0925-1030}}, language = {{eng}}, number = {{3}}, pages = {{353--366}}, publisher = {{Springer}}, series = {{Analog Integrated Circuits and Signal Processing}}, title = {{Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations}}, url = {{http://dx.doi.org/10.1007/s10470-013-0114-y}}, doi = {{10.1007/s10470-013-0114-y}}, volume = {{76}}, year = {{2013}}, }